EN25P40 Datasheet PDF - Eon
| Part Number | EN25P40 | |
| Description | 4 Mbit Uniform Sector Flash Memory | |
| Manufacturers | Eon | |
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EN25P40
4 Mbit Uniform Sector, Serial Flash Memory
EN25P40
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• 4 Mbit Serial Flash
- 4 M-bit/512 K-byte/2048 pages
- 256 bytes per programmable page
• High performance
- 75MHz clock rate
• Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
• Uniform Sector Architecture:
- Eight 64-Kbyte sectors
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Byte program time: 7µs typical
- Page program time: 1.5ms typical
- Sector erase time: 800 ms typical
- Chip erase time: 5 Seconds typical
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 150mil body width
- 8 pins SOP 200mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25P40 is a 4M-bit (512K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25P40 is designed to allow either single Sector at a time or full chip erase operation. The
EN25P40 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2006/12/25
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OPERATING FEATURES
EN25P40
SPI Modes
The EN25P40 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.
Data output on the DO pin is clocked out on the falling edge of SCK.
Figure 3. SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at
a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of
memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time,
using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)
instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be
preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE)
can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it
to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power
mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this
mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID
(RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2006/12/25
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EN25P40 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ EN25P40.PDF Datasheet ] | |
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