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EN25P05 Schematic ( PDF Datasheet ) - Eon Silicon Solution

Teilenummer EN25P05
Beschreibung 512 Kbit Uniform Sector Flash Memory
Hersteller Eon Silicon Solution
Logo Eon Silicon Solution Logo 




Gesamt 30 Seiten
EN25P05 Datasheet, Funktion
www.DataSheet4U.com
EN25P05
512 Kbit Uniform Sector, Serial Flash Memory
EN25P05
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
512 Kbit Serial Flash
- 512 K-bit/64 K-byte/256 pages
- 256 bytes per programmable page
High performance
- 75MHz clock rate
Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- Two 32-Kbyte sectors
Software and Hardware Write Protection:
GENERAL DESCRIPTION
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Byte program time: 8µs typical
- Page program time: 1.5ms typical
- Sector erase time: 500ms typical
- Chip erase time: 1 Seconds typical
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 150mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
Commercial and industrial temperature
Range
The EN25P05 is a 512 K-bit (64K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25P05 is designed to allow either single Sector at a time or full chip erase operation. The
EN25P05 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2006/12/27






EN25P05 Datasheet, Funktion
www.DataSheet4U.com
EN25P05
Status Register. The Status Register contains a number of status and control bits that can be read or set
(as appropriate) by specific instructions.
BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions.
SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in
the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP1, BP0)
become read-only bits.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25P05
provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the
Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction
completion or Bulk Erase (BE) instruction completion or
z The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is
the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP1, BP0) bits and Status Register Protect
(SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra software
protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored
except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Memory Content
BP1
Bit
1
1
0
0
BP0
Bit
1
0
1
0
Protected Sectors
Addresses
Density(KB)
Portion
All ( Sector 0 to 1)
000000h-00FFFFh 64KB
All sectors
PP(page program), and SE(sector erase) is enabled without checking address.
All sectors are protected against BE(bulk erase).
None
None
None
None
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence. However, taking this signal Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
This Data Sheet may be revised by subsequent versions
6
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2006/12/27

6 Page









EN25P05 pdf, datenblatt
www.DataSheet4U.com
EN25P05
Read Data Bytes (READ) (03h)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data
Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock
(CLK).
The instruction sequence is shown in Figure 9.. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the
highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be
continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while
an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is
in progress.
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy
byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at
that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum
frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 10.. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the
read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at
Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
This Data Sheet may be revised by subsequent versions 12 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2006/12/27

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