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PDF EN25F40 Data sheet ( Hoja de datos )
| Número de pieza | EN25F40 | |
| Descripción | 4 Mbit Serial Flash Memory | |
| Fabricantes | Eon | |
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EN25F40
EN25F40
4 Mbit Serial Flash Memory with 4Kbytes Uniform Sector
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• 4 Mbit Serial Flash
- 4 M-bit/512 K-byte/2048 pages
- 256 bytes per programmable page
• High performance
- 100MHz clock rate
• Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
• Uniform Sector Architecture:
- 128 sectors of 4-Kbyte
- 8 blocks of 64-Kbyte
- Any sector or block can be
erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Page program time: 1.5ms typical
- Sector erase time: 150ms typical
- Block erase time 800ms typical
- Chip erase time: 5 Seconds typical
• Lockable 256 byte OTP security sector
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 150mil body width
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25F40 is a 4M-bit (512K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25F40 is designed to allow either single Sector at a time or full chip erase operation. The
EN25F40 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/05/09
1 page  
www.DataSheet4U.com
OPERATING FEATURES
EN25F40
SPI Modes
The EN25F40 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.
Data output on the DO pin is clocked out on the falling edge of SCK.
Figure 3. SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at
a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of
memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time, using
the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout
the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration
tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE ) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBEor tCE). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value,
polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The device then goes into the Stand-by Power
mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this
mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID
(RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/05/09
5 Page 
www.DataSheet4U.com
EN25F40
Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0
for these bit locations. It is recommended to mask out the reserved bit when testing the Status Register.
Doing this will ensure compatibility with future devices.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to
1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP,
BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer
accepted for execution.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be
programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user
must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command
to lock the OTP sector before leaving OTP mode.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After
the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 8.. The Write Status Register (WRSR) instruction has no
effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#)
must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status
Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed
Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is
completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table
3.. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register
Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit
and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The
Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is
entered.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2007/05/09
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EN25F40.PDF ] | |
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