PDF EN25B32 Data sheet ( Hoja de datos )

Número de pieza	EN25B32
Descripción	32 Mbit Serial Flash Memory
Fabricantes	Eon
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No Preview Available ! www.DataSheet4U.com EN25B32 EN25B32 32 Mbit Serial Flash Memory with Boot and Parameter Sectors FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • 32 M-bit Serial Flash - 32 M-bit/4096 K-byte/16384 pages - 256 bytes per programmable page • High performance - 100MHz clock rate • Low power consumption - 5 mA typical active current - 1 μA typical power down current • Flexible Sector Architecture: - Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one 32-Kbyte, and sixty three 64-Kbyte sectors • Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin • High performance program/erase speed - Byte program time: 7µs typical - Page program time: 1.5ms typical - Sector erase time: 300 to 800ms typical - Chip erase time: 25 Seconds typical • Lockable 512byte OTP security sector • Minimum 100K endurance cycle • Package Options - 16 pins SOP 300mil body width - 8 pins SOP 200mil body width - 8 contact VDFN - 8 pins PDIP - All Pb-free packages are RoHS compliant • Commercial and industrial temperature Range GENERAL DESCRIPTION The EN25B32 is a 32M-bit (4096K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25B32 has sixty eight sectors including sixty three sectors of 64KB, one sector of 32KB, one sector of 16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single Sector at a time or full chip erase operation. The EN25B32 can protect boot code stored in the small sectors for either bottom or top boot configurations. The device can sustain a minimum of 100K program/erase cycles on each sector. This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications. ©2004 Eon Silicon Solution, Inc., www.essi.com.tw Rev. C, Issue Date: 2007/06/21 1 page www.DataSheet4U.com EN25B32 MEMORY ORGANIZATION The memory is organized as: z 4,194,304 bytes z Flexible Sector Architecture Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one 32-Kbyte, and sixty three 64-Kbyte sectors z Bottom or top boot configurations z 16384 pages (256 bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable but not Page Erasable. Table 2a. Bottom Boot Block Sector Architecture Sector 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SECTOR SIZE (KByte) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 3F0000h – 3FFFFFh 3E0000h – 3EFFFFh 3D0000h – 3DFFFFh 3C0000h – 3CFFFFh 3B0000h – 3BFFFFh 3A0000h – 3AFFFFh 390000h – 39FFFFh 380000h – 38FFFFh 370000h – 37FFFFh 360000h – 36FFFFh 350000h – 35FFFFh 340000h – 34FFFFh 330000h – 33FFFFh 320000h – 32FFFFh 310000h – 31FFFFh 300000h – 30FFFFh 2F0000h – 2FFFFFh 2E0000h – 2EFFFFh 2D0000h – 2DFFFFh 2C0000h – 2CFFFFh 2B0000h – 2BFFFFh 2A0000h – 2AFFFFh 290000h – 29FFFFh 280000h – 28FFFFh 270000h – 27FFFFh 260000h – 26FFFFh 250000h – 25FFFFh 240000h – 24FFFFh 230000h – 23FFFFh 220000h – 22FFFFh 210000h – 21FFFFh 200000h – 20FFFFh 1F0000h – 1FFFFFh 1E0000h – 1EFFFFh 1D0000h – 1DFFFFh 1C0000h – 1CFFFFh This Data Sheet may be revised by subsequent versions 5 or modifications due to changes in technical specifications. ©2004 Eon Silicon Solution, Inc., www.essi.com.tw Rev. C, Issue Date: 2007/06/21 5 Page www.DataSheet4U.com EN25B32 Table 3a. Protected Area Sizes- Bottom Boot Sector Organization Status Register Content BP2 BP1 BP0 Bit Bit Bit 111 110 101 100 011 010 001 000 Memory Content Protect Sectors All Sector 0 to 35 Sector 0 to 4 Sector 0 to 3 Sector 0 to 2 Sector 0 to 1 Sector 0 None Addresses 000000h-3FFFFFh 000000h-1FFFFFh 000000h-00FFFFh 000000h-007FFFh 000000h-003FFFh 000000h-001FFFh 000000h-000FFFh None Density(KB) Portion 4096KB 2048KB 64KB 32KB 16KB 8KB 4KB None All Lower 1/2 Lower 1/64 Lower 1/128 Lower 1/256 Lower 1/512 Lower 1/1024 None Table 3b. Protected Area Sizes- Top Boot Sector Organization Status Register Content BP2 BP1 BP0 Bit Bit Bit 000 001 010 011 100 101 110 111 Protect Sectors None Sector 67 Sector 66 to 67 Sector 65 to 67 Sector 64 to 67 Sector 63 to 67 Sector 32 to 67 All Memory Content Addresses Density(KB) None 3FF000h-3FFFFFh 3FE000h-3FFFFFh 3FC000h-3FFFFFh 3F8000h-3FFFFFh 3F0000h-3FFFFFh 200000h-3FFFFFh 000000h-3FFFFFh None 4KB 8KB 16KB 32KB 64KB 2048KB 4096KB Portion None Upper 1/1024 Upper 1/512 Upper 1/256 Upper 1/128 Upper 1/64 Upper 1/2 All Hold Function The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low (as shown in Figure 4.). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low. If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.). During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are Don’t Care. Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold condition. This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw or modifications due to changes in technical specifications. Rev. C, Issue Date: 2007/06/21 11 Page

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