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EP2C20 Schematic ( PDF Datasheet ) - Altera

Teilenummer EP2C20
Beschreibung ISDN Line Interface
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EP2C20 Datasheet, Funktion
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Section IV. I/O Standards
This section provides information on CycloneII single-ended, voltage
referenced, and differential I/O standards.
This section includes the following chapters:
Chapter 10, Selectable I/O Standards in Cyclone II Devices
Chapter 11, High-Speed Differential Interfaces in Cyclone II Devices
Revision History The table below shows the revision history for Chapters 10 and 11.
Chapter(s) Date / Version
Changes Made
10 November 2004, Updated Table 10–7.
v1.1
www.DataSheet4U.comJune 2004, v1.0 Added document to the Cyclone II Device
Handbook.
11 November 2004, Updated Table 11–1.
v1.1 Updated Figures 11–4, 11–5, 11–7, and
11–8.
June 2004, v1.0 Added document to the Cyclone II Device
Handbook.
Altera Corporation
Section IV–1
Preliminary
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EP2C20 Datasheet, Funktion
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Supported I/O Standards
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVCMOS I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVCMOS standard defines the
DC interface parameters for digital circuits operating from a 3.0- or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input voltage requirements as
LVTTL (– 0.3 V VI 3.9 V). The output buffer drives to the rail to meet
the minimum high-level output voltage requirements. The 3.3-V I/O
standard does not require input reference voltages or board terminations.
Cyclone II devices support both input and output levels specified by the
3.3-V LVCMOS I/O standard.
3.3-V (PCI Special Interest Group [SIG] PCI Local Bus
Specification Revision 3.0)
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
www.DataSheet4U.comspecification revision 3.0 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires a 3.3-V VCCIO. The 3.3-V PCI standard does not require input
reference voltages or board terminations.
The side (left and right) I/O banks on all Cyclone II devices are fully
compliant with the 3.3V PCI Local Bus Specification Revision 3.0 and meet
32-bit/66 MHz operating frequency and timing requirements.
Table 10–2 lists the specific Cyclone II devices that support 64- and 32-bit
PCI at 66 MHz.
Table 10–2. Cyclone II 66-MHz PCI Support (Part 1 of 2)
Device
EP2C5
EP2C8
Package
144-pin TQFP
208-pin PQFP
144-pin TQFP
208-pin PQFP
256-pin FineLine BGA®
-6 & -7 Speed Grades
64 Bits
32 Bits
v
v
v
10–4
Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation
November 2004
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6 Page









EP2C20 pdf, datenblatt
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Supported I/O Standards
The 1.8-V standard does not require input reference voltages or board
terminations. Cyclone II devices support input and output levels for both
normal and wide 1.8-V LVCMOS ranges.
SSTL-18 Class I & II
The 1.8-V SSTL-18 standard is formulated under JEDEC Standard,
JESD815: Stub Series Terminated Logic for 1.8V (SSTL-18).
The SSTL-18 I/O standard is a 1.8-V memory bus standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT, with the
termination resistors connected to both. There are no class definitions for
the SSTL-18 standard in the JEDEC specification. The specification of this
I/O standard is based on an environment that consists of both series and
parallel terminating resistors. Altera provides solutions to two derived
applications in JEDEC specification and names them class I and class II to
be consistent with other SSTL standards. Figures 10–5 and 10–6 show
SSTL-18 class I and II termination, respectively. Cyclone II devices
support both input and output levels.
www.DataSheet4U.comFigure 10–5. 1.8-V SSTL Class I Termination
Output Buffer
25
VTT = 0.9 V
Z = 50
50
Input Buffer
VREF = 0.9 V
Figure 10–6. 1.8-V SSTL Class II Termination
VTT = 0.9 V
VTT = 0.9 V
Output Buffer
50
50
25
Z = 50
VREF = 0.9 V
Input Buffer
10–10
Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation
November 2004
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12 Page





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