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AD5449 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5449
Beschreibung (AD54x9) Bandwidth Multiplying DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5449 Datasheet, Funktion
FEATURES
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Pin compatible 8-, 10-, and 12-bit DACs
Extended temperature range: −40°C to +125°C
16-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Dual 8-,10-,12-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5429/AD5439/AD5449
VDD
SYNC
SCLK
SDIN
SDO
CLR
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5429/AD5439/AD5449
RFB
R
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC A
POWER-ON
RESET
INPUT
REGISTER
LDAC
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC B
LDAC
Figure 1.
VREFB
RFB
R
RFBA
IOUT1A
IOUT2A
IOUT1B
IOUT2B
RFBB
GENERAL DESCRIPTION
The AD5429/AD5439/AD54491 are CMOS 8-, 10-, and 12-bit
dual-channel current output digital-to-analog converters,
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros and the DAC outputs
are at zero scale.
As a result of manufacture on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication character-
istics, with large signal multiplying bandwidths of 10 MHz.
The AD5429/AD5439/AD5449 DAC are available in 16-lead
TSSOP packages.
1 US Patent Number 5,689,257.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD5449 Datasheet, Funktion
AD5429/AD5439/AD5449
SCLK
SYNC
DIN
LDAC1
LDAC2
t8 t4
DB15
t6
t5
t1
t2 t3
t7
DB0
t9
t10
t11
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
SCLK
SYNC
SDIN
SDO
t4
DB15
(N)
t6
t5
t1
t2 t3
DB0
(N)
t12
DB15
(N+1)
DB15
(N)
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
t7
DB0
(N+1)
t8
DB0
(N)
200µA
IOL
TO OUTPUT
PIN CL
50pF
VOH (MIN) + VOL (MAX)
2
200µA
IOH
Figure 4. Load Circuit for SDO Timing Specifications
Rev. 0 | Page 6 of 32

6 Page









AD5449 pdf, datenblatt
AD5429/AD5439/AD5449
14
TA = 25°C
LOADING ZS TO FS
12
10
VDD = 5V
8
6 VDD = 3V
4
VDD = 2.5V
2
0
1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 18. Supply Current vs. Update Rate
6
0
TA = 25°C
LOADING
–6 ZS TO FS
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
1
10
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ALL OFF
TA = 25°C
VDD = 5V
VREF = ±3.5V
INPUT
CCOMP = 1.8pF
AD8038 AMPLIFIER
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 19. Reference Multiplying Bandwidth vs. Frequency and Code
0.2
0
–0.2
–0.4
–0.6
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
–0.8
1 10 100 1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 20. Reference Multiplying Bandwidth–All 1s Loaded
3
TA = 25°C
VDD = 5V
0
–3
–6
–9
10k
VREF = ±2V, AD8038 CC 1.47pF
VREF = ±2V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1.47pF
VREF = ±3.51V, AD8038 CC 1.8pF
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 21. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
0.045
0.040
0.035
7FF TO 800H
VDD = 5V
0.030
TA = 25°C
VREF = 0V
AD8038 AMPLIFIER
CCOMP = 1.8pF
0.025
0.020
VDD = 3V
0.015
0.010
0.005
800 TO 7FFH
VDD = 3V
0
–0.005
–0.010
0
VDD = 5V
20 40 60 80 100 120 140 160 180 200
TIME (ns)
Figure 22. Midscale Transition, VREF = 0 V
–1.68
–1.69
–1.70
7FF TO 800H
VDD = 5V
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
CCOMP = 1.8pF
–1.71
–1.72
–1.73
–1.74
–1.75
VDD = 3V
VDD = 5V
VDD = 3V
–1.76
–1.77
0
800 TO 7FFH
20 40 60
80 100 120 140 160 180 200
TIME (ns)
Figure 23. Midscale Transition, VREF = 3.5 V
Rev. 0 | Page 12 of 32

12 Page





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