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PDF AD8372 Data sheet ( Hoja de datos )
| Número de pieza | AD8372 | |
| Descripción | Programmable Dual VGA | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Dual independent digitally controlled VGA
Differential input and output
150 Ω differential input
Open-collector differential output
7.8 dB noise figure to 100 MHz @ maximum gain
HD2/HD3 better than 77 dBc for 1 V p-p differential output
−3 dB bandwidth of 130 MHz
41 dB gain range
1 dB step size ± 0.2 dB
Serial 8-bit bidirectional SPI control interface
Wide input dynamic range
Pin-programmable output stage
Power-down feature
Single 5 V supply: 106 mA per channel
32-lead LFCSP, 5 mm × 5 mm package
APPLICATIONS
Differential ADC drivers
CMTS upstream direct sampling receivers
CATV modem signal scaling
Generic RF/IF gain stages
Single-ended-to-differential conversion
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain
amplifier (VGA) that provides precise gain control, high IP3,
and low noise figure. The excellent distortion performance and
moderate signal bandwidth make the AD8372 a suitable
gain control device for a variety of multichannel receiver
applications.
For wide input dynamic range applications, the AD8372
provides a broad 41 dB gain range. The gain is programmed
through a bidirectional 4-pin serial interface. The serial inter-
face consists of a clock, latch, data input, and data output lines
for each channel.
The AD8372 provides the ability to set the transconductance of
the output stage using a single external resistor. The RXT1 and
RXT2 pins provide a band gap derived stable reference voltage
of 1.56 V. Typically 2.0 kΩ shunt resistors to ground are used to
set the maximum gain to a nominal value of 31 dB. The current
41 dB Range, 1 dB Step Size,
Programmable Dual VGA
AD8372
FUNCTIONAL BLOCK DIAGRAM
ENB1
IPC1
INC1
RXT1
AD8372
CHANNEL 1 POSTAMP
REF1
OPC1
ONC1
CLK1
SDO1
SDI1
LCH1
RXT2
IPC2
INC2
ENB2
REGISTERS
AND
GAIN DECODER
CHANNEL 2
POSTAMP
Figure 1.
CLK2
SDO2
SDI2
LCH2
OPC2
ONC2
REF2
setting resistors can be adjusted to manipulate the gain and
distortion performance of each channel. This is a flexible
feature in applications where it is desirable to trade off distortion
performance for lower power consumption.
The AD8372 is powered on by applying the appropriate logic
level to the ENB1, ENB2 pins. When powered down, the AD8372
consumes less than 2.6 mA and offers excellent input-to-output
isolation. The gain setting is preserved when powered down.
Fabricated on an Analog Devices, Inc., high frequency BiCMOS
process, the AD8372 provides precise gain adjustment capabilities
with good distortion performance. The quiescent current of the
AD8372 is typically 106 mA per channel. The AD8372 amplifier
comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead
LFCSP package and operates over the temperature range of
−40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD8372
Parameter
POWER INTERFACE
Supply Voltage
Quiescent Current per Channel
vs. Temperature
Power-Down Current, Both Channels
vs. Temperature
ENABLE INTERFACE
Enable Threshold
ENB1, ENB2 Input Bias Current
GAIN CONTROL INTERFACE
VIH
Input Bias Current
Serial Port Output Feedthrough
Conditions
Min Typ Max Unit
Thermal connection made to exposed paddle under
device
−40°C ≤ TA ≤ +85°C
ENB1 and ENB2 low
−40°C ≤ TA ≤ +85°C
Pin ENB1 and Pin ENB2
Minimum voltage to enable the device
ENB1, ENB2 = 0 V
Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin
SDO2, Pin LCH1, and Pin LCH2
Minimum voltage for a logic high
4.5
2.4
Worse-case feedthrough from CLK1, CLK2, SDI1,
SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2,
or OPC2 and ONC2
5.5
106
135
1.2
1.3
0.8
400
400
−60
V
mA
mA
mA
mA
V
nA
V
nA
dB
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code1
Voltage Gain (dB)
RW DC 000000
< −60
RW DC 000001
−9
RW DC 000010
−8
RW DC 000011
−7
RW DC 000100
−6
RW DC 000101
−5
RW DC 000110
−4
RW DC 000111
−3
RW DC 001000
−2
RW DC 001001
−1
RW DC 001010
0
RW DC 001011
+1
RW DC 001100
+2
RW DC 001101
+3
RW DC 001110
+4
RW DC 001111
+5
RW DC 010000
+6
RW DC 010001
+7
RW DC 010010
+8
RW DC 010011
+9
RW DC 010100
+10
RW DC 010101
+11
1 RW is the read/write bit. RW = 0 for read mode; RW = 1 for write mode. DC is
the don’t care bit.
8-Bit Binary Gain Code1
RW DC 010110
RW DC 010111
RW DC 011000
RW DC 011001
RW DC 011010
RW DC 011011
RW DC 011100
RW DC 011101
RW DC 011110
RW DC 011111
RW DC 100000
RW DC 100001
RW DC 100010
RW DC 100011
RW DC 100100
RW DC 100101
RW DC 100110
RW DC 100111
RW DC 101000
RW DC 101001
RW DC 101010
RW DC 101011
Voltage Gain (dB)
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+32
< −60
Rev. B | Page 4 of 16
5 Page 
AD8372
THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each
amplifier consists of a 150 Ω digitally controlled 6 dB attenuator
followed by a 1 dB vernier and a fixed gain transconductance
amplifier.
The differential output on each amplifier consists of a pair of
open-collector transistors. It is recommended that each open-
collector output be biased to +5 V with a high value inductor.
A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an
excellent choice for this component. A 250 Ω resistor should be
placed across the differential outputs to provide a current-to-
voltage conversion and as a source impedance for passive
filtering, post AD8372.
The gain for each side is based on a 250 Ω differential load and
varies as the RLOAD changes per the following equations:
Gain = 20log(RLOAD/250), for voltage gain
Gain = 10log(RLOAD/250), for power gain
The dependency of the gain on the load is due to the open-
collector output stage that is biased using external chokes. The
inductance of the chokes and the resistance of the load deter-
mine the low frequency pole of the amplifier. The high frequency
pole is set by the parasitic capacitance of the chokes and outputs
in parallel with the output resistance.
The total supply current of 106 mA per side consists of 70 mA
for the combined outputs and about 36 mA through the power
supply pins. Each side has an external resistor (REXT) to ground
to set the transconductance of the output stage. For optimum
distortion, 106 mA total current per side is recommended,
making the REXT value about 2.0 kΩ. Each side has a 2.4 V
reference pin and that same common-mode voltage appears on
the inputs. This reference should be decoupled using a 0.1 μF
capacitor. The part can be powered down to less than 2.6 mA by
setting the ENB pin low for the appropriate side.
The noise figure of the AD8372 is 7.8 dB at maximum gain and
increases as the gain is reduced. The increase in noise figure is
equal to the reduction in gain.
The linearity of the part measured at the output is first-order
independent of the gain setting.
Layout considerations should include minimizing capacitance
on the outputs by avoiding ground planes under the chokes, and
equalizing the output line lengths for phase balance.
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
The AD8372 is designed to be used by applying differential
signals to the inputs and using the differential output drive of
the device to drive the next device in the signal chain. The
excellent distortion performance of the AD8372 is due
primarily to the use of differential signaling techniques to
cancel various distortion components in the device. In addition,
all ac characterization is done using differential signal paths.
Using this device with either the input or the output in a single-
ended circuit significantly degrades the overall performance of
the AD8372.
PASSIVE FILTER TECHNIQUES
The AD8372 has a 100 Ω differential input impedance. For
optimal performance, the differential output load should be
250 Ω. When designing passive filters around the AD8372,
these impedances must be taken into account.
DIGITAL GAIN CONTROL
The digital gain control interface consists of the following pins:
SDI, SDO, CLK, and LATCH. The interface is active when the
LATCH pin is shifted low. Gain words are written into the
AD8372 via the SDI pin, and read back from the SDO pin. The
first bit clocked into the data input pin determines whether the
interface is in write or read mode. The second bit is a don’t care
bit, while the remaining six bits program the gain. In read
mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB.
The gain can be programmed between −9 dB and 32 dB in 1 dB
steps. Timing details are given in Figure 2 and Figure 3. The
gain code is given in Table 2.
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The AD8372 is designed with the intention of driving high
speed, high dynamic range ADCs. The circuit in Figure 14
represents a simplified front end of one-half of the AD8372 dual
VGA driving an AD9445 14-bit, 125 MHz analog-to-digital
converter (ADC). The input of the AD8372 is driven
differentially using a 1:3 impedance ratio transformer, which
also matches the 150 Ω input resistance to a 50 Ω source. The
open-collector outputs are biased through the 33 μH inductors
and are ac-coupled from the 142 Ω load resistors that, in
parallel with the 2 kΩ input resistance of the ADC, provide a
250 Ω load for gain accuracy.
The ADC is ac-coupled from the 142 Ω resistors to negate a dc
effect on the input common-mode voltage of the AD9445.
Including the series 33 Ω resistors improves the isolation of the
AD8372 from the switching currents caused by the ADC input
sample and hold. The AD9445 represents a 2 kΩ differential
load and requires a 2 V p-p signal when VREF = 1 V for a full-
scale output. This circuit provides variable gain, isolation, and
source matching for the AD9445. Using this circuit with the
AD8372 in a gain of 32 dB (maximum gain), an SFDR
performance of 74.5 dBc is achieved at 85 MHz (see Figure 15).
Rev. B | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD8372.PDF ] | |
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