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GS864018T-xxxV Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS864018T-xxxV
Beschreibung 72Mb Sync Burst SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 23 Seiten
GS864018T-xxxV Datasheet, Funktion
GS864018/32/36T-xxxV
100-Pin TQFP
Commercial Temp
Industrial Temp
4M x 18, 2M x 32, 2M x 36
72Mb Sync Burst SRAMs
250 MHz167 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS864018/32/36T-xxxV is a 75,497,472-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS864018/32/36T-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 1.8 V or 2.5 V
compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-250 -200 -167 Unit
2.5 3.0 3.4 ns
4.0 5.0 6.0 ns
340 290 260 mA
410 350 305 mA
6.5 7.5 8.0 ns
6.5 7.5 8.0 ns
245 220 210 mA
280 250 240 mA
Rev: 1.03a 2/2009
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology






GS864018T-xxxV Datasheet, Funktion
A0An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
GS864018/32/36T-xxxV Block Diagram
GS864018/32/36T-xxxV
Register
DQ
A0
A1
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
A
Memory
Array
QD
Register
DQ
Register
DQ
36
4
36
Register
DQ
Register
DQ
E1
E2
E3
FT
G
ZZ Power Down
Control
Note: Only x36 version shown for simplicity.
Register
DQ
Register
DQ
SCD
DQx1DQx9
Rev: 1.03a 2/2009
6/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

6 Page









GS864018T-xxxV pdf, datenblatt
GS864018/32/36T-xxxV
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
0.5 to 4.6
V
VDDQ
Voltage on VDDQ Pins
0.5 to VDD
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ +0.5 (4.6 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDD +0.5 (4.6 V max.)
V
IIN Input Current on Any Pin
+/20
mA
IOUT Output Current on Any I/O Pin
+/20
mA
PD Package Power Dissipation
1.5 W
TSTG Storage Temperature
55 to 125
oC
TBIAS
Temperature Under Bias
55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version)
Parameter
Symbol Min. Typ. Max. Unit Notes
1.8 V Supply Voltage
VDD1
1.7
1.8
2.0
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
1.8 V VDDQ I/O Supply Voltage
VDDQ1
1.7
1.8 VDD
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5 VDD
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.03a 2/2009
12/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

12 Page





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