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GS864236B-xxxV Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS864236B-xxxV
Beschreibung (GS8642xxB/C-xxxV) 4M x 18 / 2M x 36/ 1M x 72 72Mb S/DCD Sync Burst SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS864236B-xxxV Datasheet, Funktion
www.DataSheet4U.com
Preliminary
GS864218/36/72(B/C)-xxxV
119- & 209-Pin BGA
Commercial Temp
Industrial Temp
4M x 18, 2M x 36, 1M x 72
72Mb S/DCD Sync Burst SRAMs
250 MHz167 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
• RoHS-compliant 119- and 209-bump BGA packages available
Functional Description
Applications
The GS864218/36/72(B/C)-xxxV is a 75,497,472-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS864218/36/72(B/C)-xxxV is a SCD (Single Cycle
Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous
SRAM. DCD SRAMs pipeline disable commands to the same
degree as read commands. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command
has been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure this SRAM for either mode of operation using the
SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Core and Interface Voltages
The GS864218/36/72(B/C)-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise from
the internal circuits and are 1.8 V or 2.5 V compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-250 -200 -167 Unit
tKQ)
tCycle
3.0 3.0 3.5 ns
4.0 5.0 6.0 ns
Curr (x18)
Curr (x36)
Curr (x72)
340 290 260 mA
410 350 305 mA
520 435 380 mA
tKQ
tCycle
6.5 7.5 8.0 ns
6.5 7.5 8.0 ns
Curr (x18)
Curr (x36)
Curr (x72)
245 220 210 mA
280 250 240 mA
370 315 300 mA
Rev: 1.03 6/2006
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology






GS864236B-xxxV Datasheet, Funktion
www.DataSheet4U.com
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Preliminary
GS864218/36/72(B/C)-xxxV
119-Bump BGA—x18 Common I/O—Top View (Package B)
1234567
VDDQ
A
A ADSP A
A VDDQ
NC A
A ADSC A
A NC
NC A
A VDD A
A NC
DQB NC VSS ZQ VSS DQPA NC
NC DQB VSS E1 VSS NC DQA
VDDQ
NC
VSS
G
VSS DQA VDDQ
NC DQB BB ADV NC
NC DQA
DQB NC VSS GW VSS DQA NC
VDDQ
VDD
NC
VDD
NC
VDD VDDQ
NC DQB VSS CK VSS NC DQA
DQB NC
NC SCD BA DQA NC
VDDQ
DQB
VSS
BW
VSS
NC VDDQ
DQB NC VSS A1 VSS DQA NC
NC DQPB VSS A0 VSS NC DQA
NC A LBO VDD FT A NC
A A A A A A ZZ
VDDQ
TMS
TDI
TCK TDO
NC
VDDQ
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
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Rev: 1.03 6/2006
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

6 Page









GS864236B-xxxV pdf, datenblatt
www.DataSheet4U.com
Simplified State Diagram
Preliminary
GS864218/36/72(B/C)-xxxV
X
Deselect
WR
WR
X First Write R
CW CR
First Read
X
CR
W
R
X Burst Write
CR
CW
R
Burst Read
X
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.03 6/2006
12/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

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