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PDF GS8662R09E-xxx Data sheet ( Hoja de datos )
| Número de pieza | GS8662R09E-xxx | |
| Descripción | (GS8662RxxE-xxx) 72Mb SigmaCIO DDR-II Burst of 4 SRAM | |
| Fabricantes | GSI Technology | |
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Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaCIO DDR-II
Burst of 4 SRAM
333 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and future
144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaCIO™ Family Overview
The GS8662R08/09/18/36E are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs
always transfer data in four packets. When a new address is
loaded, A0 and A1 preset an internal 2 bit linear address
counter. The counter increments by 1 for each beat of a burst of
four data transfer. The counter always wraps to 00 after
reaching 11, no matter where it starts.
Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer
data in four packets. When a new address is loaded, the LSBs
are internally set to 0 for the first read or write transfer, and
incremented by 1 for the next 3 transfers. Because the LSBs
are tied off internally, the address field of a x8 SigmaCIO
DDR-II B4 RAM is always two address pins less than the
advertised index depth (e.g., the 4M x 18 has a 1024K
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.01 9/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
1 page  
www.DataSheet4U.com
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
8M x 8 SigmaCIO DDR-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A CQ SA SA R/W NW1 K NC LD SA SA CQ
B NC NC NC SA NC K NW0 SA NC NC DQ3
C NC NC NC VSS SA NC SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA C SA SA NC NC NC
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7
3. MCL = Must Connect Low
Rev: 1.01 9/2005
5/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
5 Page 
www.DataSheet4U.com
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
Common I/O SigmaCIO DDR-II B4 SRAM Truth Table
DQ
Kn LD R/W
A+0
A+1
A+2
↑ 1 X Hi-Z
↑ 0 0 D@Kn+1
Q@Kn+1
↑ 0 1 or
Cn+1
Note:
Q is controlled by K clocks if C clocks are not used.
Hi-Z
D@Kn+1
Q@Kn+2
or
Cn+2
Hi-Z
D@Kn+2
Q@Kn+2
or
Cn+2
A+3
Hi-Z
D@Kn+2
Q@Kn+3
or
Cn+3
Operation
Deselect
Write
Read
Rev: 1.01 9/2005
11/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
11 Page | ||
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