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GS8662R08E-xxx Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8662R08E-xxx
Beschreibung (GS8662RxxE-xxx) 72Mb SigmaCIO DDR-II Burst of 4 SRAM
Hersteller GSI Technology
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Gesamt 30 Seiten
GS8662R08E-xxx Datasheet, Funktion
www.DataSheet4U.com
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaCIO DDR-II
Burst of 4 SRAM
333 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and future
144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaCIOFamily Overview
The GS8662R08/09/18/36E are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs
always transfer data in four packets. When a new address is
loaded, A0 and A1 preset an internal 2 bit linear address
counter. The counter increments by 1 for each beat of a burst of
four data transfer. The counter always wraps to 00 after
reaching 11, no matter where it starts.
Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer
data in four packets. When a new address is loaded, the LSBs
are internally set to 0 for the first read or write transfer, and
incremented by 1 for the next 3 transfers. Because the LSBs
are tied off internally, the address field of a x8 SigmaCIO
DDR-II B4 RAM is always two address pins less than the
advertised index depth (e.g., the 4M x 18 has a 1024K
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.01 9/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology






GS8662R08E-xxx Datasheet, Funktion
www.DataSheet4U.com
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW3
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
LD Synchronous Load Pin
K Input Clock
K Input Clock
C Output Clock
C Output Clock
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock Input
TDO Test Data Output
VREF HSTL Input Reference Voltage
ZQ Output Impedance Matching Input
MCL Must Connect Low
DQ Data I/O
Doff Disable DLL when low
CQ Output Echo Clock
CQ Output Echo Clock
VDD Power Supply
VDDQ
Isolated Output Buffer Supply
VSS Power Supply: Ground
Note:
NC = Not Connected to die or any other pin
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input/Output
Input
Output
Output
Supply
Supply
Supply
Comments
Active High
Active Low
Active Low
x18/x36 only
Active Low
x8 only
Active Low
Active High
Active Low
Active High
Active Low
Three State
Active Low
1.8 V Nominal
1.5 V Nominal
Rev: 1.01 9/2005
6/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

6 Page









GS8662R08E-xxx pdf, datenblatt
www.DataSheet4U.com
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
B4 Byte Write Clock Truth Table
BW BW BW BW
Current Operation
DDDD
KKKK
KKKKK
(tn+1)
(tn+1½)
(tn+2)
(tn+2½)
(tn)
(tn+1) (tn+1½) (tn+2) (tn+2½)
T
T
T
T
Write
Dx stored if BWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
F
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
X D2 X
F
F
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
X
X D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
Rev: 1.01 9/2005
12/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

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