|
|
PDF AK4555 Data sheet ( Hoja de datos )
| Número de pieza | AK4555 | |
| Descripción | Low Power & Small Package 20bit CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AK4555 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
ASAHI KASEI
[AK4555]
AK4555
Low Power & Small Package 20bit ∆Σ CODEC
GENERAL DESCRIPTION
The AK4555 is a low voltage 20bit A/D & D/A converter for portable digital audio system. In the AK4555,
the loss of accuracy form clock jitter is also improved by using SCF techniques for on-chip post filter.
Analog signal input/output of the AK4555 are single-ended, therefore, any external filters are not required.
The AK4555 is suitable for portable digital audio system, as the AK4555 is low power dissipation and a
small package.
FEATURES
HPF for DC-offset cancel (fc=3.4Hz)
Single-ended ADC
- S/(N+D): 80dB@VDD=2.5V
- Dynamic Range, S/N: 89dB@VDD=2.5V
Single-ended DAC
- Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling
- S/(N+D): 85dB@VDD=2.5V
- Dynamic Range, S/N: 92dB@VDD=2.5V
Audio I/F format: MSB First, 2’s Compliment
- ADC, DAC: I2S
Input/Output Voltage: 0.6 x VDD (=1.5Vpp@VDD=2.5V)
High Jitter Tolerance
Sampling Rate: 8kHz to 50kHz
Master Clock: 256fs/384fs/512fs/768fs (fs=8kHz to 50kHz)
1024fs (fs=8kHz to 25kHz)
Power Supply: 1.6 to 3.6V
Low Power Supply Current: 8.6mA
Ta = −40 to 85°C
Very Small Package: 16pin TSSOP
VDD VSS
AINL
AINR
∆Σ
Modulator
∆Σ
Modulator
VCOM
Common Voltage
Decimation
Filter
Decimation
Filter
Clock
Divider
Serial I/O
Interface
AOUTL
AOUTR
LPF
LPF
∆Σ
Modulator
∆Σ
Modulator
8X
Interpolator
8X
Interpolator
MCLK
LRCK
SCLK
SDTO
SDTI
DEM0
DEM1
PWDAN
PWADN
MS0363-E-01
-1-
2005/08
1 page  
www.DataSheet4U.com
ASAHI KASEI
[AK4555]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=2.5V; fs=44.1kHz; Signal Frequency=1kHz; SCLK=64fs; Measurement frequency=20Hz ∼ 20kHz;
unless otherwise specified)
Parameter
min typ max Units
ADC Analog Input Characteristics: (Note 2)
Resolution
- - 20 Bits
S/(N+D)
(−0.5dB Input)
70 80
- dB
D-Range
(−60dB Input, A-weighted)
82 89
- dB
S/N (A-weighted)
82 89
- dB
Interchannel Isolation
80 95
- dB
Interchannel Gain Mismatch
- 0.2 0.5 dB
Input Voltage
(Note 3)
1.35 1.50 1.65 Vpp
Input Resistance
40 70
- kΩ
Power Supply Rejection
(Note 4)
- 45 - dB
DAC Analog Output Characteristics:
Resolution
- - 20 Bits
S/(N+D)
75 85
- dB
D-Range
(−60dB Output, A-weighted)
86 92
- dB
S/N (A-weighted)
86 92
- dB
Interchannel Isolation
80 95
- dB
Interchannel Gain Mismatch
- 0.2 0.5 dB
Output Voltage
(Note 3)
1.35 1.5 1.65 Vpp
Load Resistance
10 -
- kΩ
Load Capacitance
- - 30 pF
Power Supply Rejection
(Note 4)
- 50 - dB
Power Supplies
Power Supply Current
AD+DA
PWADN= “H”, PWDAN= “H”
-
8 13 mA
AD
PWADN= “H”, PWDAN= “L”
-
4
- mA
DA
PWADN= “L”, PWDAN= “H”
-
4.4
- mA
Power down (Note 5) PWADN= “L”, PWDAN= “L”
-
10 50 µA
Power Consumption
AD+DA
PWADN= “H”, PWDAN= “H”
-
20 32.5 mW
AD
PWADN= “H”, PWDAN= “L”
-
10
- mW
DA
PWADN= “L”, PWDAN= “H”
-
11
- mW
Power down (Note 5) PWADN= “L”, PWDAN= “L”
-
25 125 µW
Note 2. The offset of ADC is removed by internal HPF.
Note 3. Input/Output of ADC and DAC scales with VDD voltage. 0.6 x VDD(typ).
Note 4. PSR is applied to VDD with 1kHz, 50mV. No signal is input to AINL/R pins and “0” data is input to SDTI pin.
Note 5. In case of power-down mode, all digital input including clocks pins (MCLK, SCLK and LRCK) are held to VDD
or VSS. PWADN and PWDAN pins are held to VSS.
MS0363-E-01
-5-
2005/08
5 Page 
www.DataSheet4U.com
ASAHI KASEI
[AK4555]
Power-down & Reset
The ADC and DAC of AK4555 are placed in the power-down mode by bringing each power down pin, PWADN,
PWDAN = “L” independently and each digital filter is also reset at the same time. These resets should always be done
after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the
output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC
operation. Figure 5 shows the power-up sequence when the ADC is powered up before the DAC power-up.
PWADN
ADC Internal
State
PWDAN
Normal Operation
Power-down
2081/fs
Init Cycle
Normal Operation
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
External
Mute
Normal Operation
GD
Power-down
Normal Operation
Idle Noise
GD
“0”data
“0”data
Idle Noise
GD
The clocks may be stopped.
Mute ON
Figure 5. Power-up Sequence
GD
MS0363-E-01
- 11 -
2005/08
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AK4555.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AK4550 | Low Power & Small Package 16-bit CODEC | Asahi Kasei Microsystems |
| AK4551 | LOW POWER & SMALL PACKAGE 20BIT CODEC | Asahi Kasei Microsystems |
| AK4552 | 3V 96KHZ 24BIT CODEC | Asahi Kasei Microsystems |
| AK4552-A | 24bit A/D and D/A converter | Asahi Kasei Microsystems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |