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ADSP21msp58 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP21msp58
Beschreibung (ADSP21msp58 / ADSP21msp59) DSP Microcomputers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP21msp58 Datasheet, Funktion
a
FEATURES
38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz
Crystal
ADSP-2100 Family Code and Function Compatible with
New Instruction Set Enhanced for Bit Manipulation
Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
2K ؋ 24 Words of On-Chip Program Memory RAM
2K ؋ 16 Words of On-Chip Data Memory RAM
4K ؋ 24 Words of On-Chip Program Memory ROM
(ADSP-21msp59 Only)
8-Bit Parallel Host Interface Port
Analog Interface Provides:
16-Bit Sigma-Delta ADC and DAC
Programmable Gain Stages
On-Chip Anti-Aliasing & Anti-Imaging Filters
8 kHz Sampling Frequency
65 dB ADC, SNR and THD
72 dB DAC, SNR and THD
425 mW Typical Power Dissipation @ 5.0 V @ 38 ns
<1 mW Powerdown Mode with 100 Cycle Recovery
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides:
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware, One Serial Port (SPORT0) has Automatic
Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (ADSP-21msp59 Only)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
100-Lead TQFP
DSP Microcomputers
ADSP-21msp58/59
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY
ADSP-21msp59
ADSP-21msp58/59
PROGRAM
MEMORY
4K x 24
(ROM)
PROGRAM DATA
MEMORY MEMORY
2K x 24
2K x 16
POWERDOWN
CONTROL
LOGIC
FLAG
ANALOG
INTERFACE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
TIMER
SERIAL PORTS
SPORT 0 SPORT 1
HOST
INTERFACE
PORT
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
GENERAL DESCRIPTION
The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Pro-
cessors (MSProcessor® DSPs) are fully integrated, single-chip
DSPs complete with a high performance analog front end. The
ADSP-21msp58/59 Family is optimized for voice band applica-
tions such as Speech Compression, Speech Processing, Speech
Recognition, Text-to Speech, and Speech-to-Text conversion.
The ADSP-21msp58/59 combines the ADSP-2100 base archi-
tecture (three computation units, data address generators, and
program sequencer) with two serial ports, a host interface port,
an analog front end, a programmable timer, extensive interrupt
capability, and on-chip program and data memory.
The ADSP-21msp58 provides 2K words (24-bit) of program
RAM and 2K words (16-bit) of data memory. The ADSP-
21msp59 provides an additional 4K words (24-bit) of program
ROM. The ADSP-21msp58/59 integrates a high performance
analog codec based on a single chip, voice band codec, the
AD28msp02. Powerdown circuitry is also provided to meet the
low power needs of battery operated portable equipment. The
ADSP-21msp58/59 is available in a 100-pin TQFP package
(thin quad flat package).
In addition, the ADSP-21msp58/59 supports new instructions,
which include bit manipulations–bit set, bit clear, bit toggle,
bit test–new ALU constants, new multiplication instruction
(x squared), biased rounding, and global interrupt masking.
MSProcessor is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADSP21msp58 Datasheet, Funktion
ADSP-21msp58/59
CLOCK OR
CRYSTAL
ANALOG
INPUT
ANALOG
OUTPUT
HIP CONTROL
HIP DATA/ADDR
12
3
4 4 5 378
CLKIN XTAL VCC GNDA
VDD GND HOST HIP
MODE
CLKOUT
RESET
SERIAL
PORT 0
IRQ2
BR ADSP-21msp58/59
BG
MMAP
FL0
SERIAL
PORT 1
PMS
RD WR ADDRESS DATA DMS BMS
SCLK
RFS
TFS
DT
DR
SCLK
RFS OR IRQ0
TFS OR IRQ1
DT OR FO
DR OR FI
14 24
HOST
PROCESSOR
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
D23-22
24
D23-8
14 2 D15-8
16 8
A D CS
OE
WE
PROGRAM
MEMORY
(OPTIONAL)
A
OE
D CS
WE DATA
MEMORY &
PERIPHERALS
(OPTIONAL)
AD
OE BOOT
MEMORY
e.g., EPROM
27C64
27C128
27C256
27C512
CS
NOTE: The two MSBs of the Boot EPROM Address are also the two MSBs of the Data Bus.
This is only for the 27C256 and 27C512.
Figure 3. ADSP-21msp58/59 Basic System Configuration
CLKOUT signal is enabled and disabled by the CLKODIS bit
in the SPORT0 Autobuffer Control Register, DM[0x3FF3].
Because the ADSP-21msp58/59 includes an on-chip oscillator
circuit, an external crystal may also be used. The crystal should
be connected across the CLKIN and XTAL pins, with two ca-
pacitors connected as shown in Figure 4. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
CLKIN
XTAL
ADSP-21msp58/59
CLKOUT
Figure 4. External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-
21msp58/59. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET dur-
ing initial power-up must be held long enough to allow the
processor’s internal clock to stabilize. If RESET is asserted at
any time after power-up, the clock continues to run and does
not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles will ensure that the PLL has locked (this
does not, however, include the crystal oscillator start-up time).
During this power-up sequence, the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master RESET sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus re-
quest and the chip is configured for booting (MMAP = 0), the
boot loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000 and ex-
ecution begins.
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single exter-
nal data bus and a single external address bus. The data and
address busses are three-stated when the DSP runs from inter-
nal memory. Refer to the ADSP-2100 Family User’s Manual,
Chapter 10, “Memory Interface” for a detailed explanation. The
14-bit address bus directly addresses up to 16K words. See
“Program Memory Maps” for details on program memory
addressing.
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and is used as a write strobe.
–6– REV. 0

6 Page









ADSP21msp58 pdf, datenblatt
ADSP-21msp58/59
ASTAT
7 6 5 4 32 10
00000000
AZ ALU Result Zero
AN ALU Result Negative
AV ALU Overflow
AC ALU Carry
AS ALU X Input Sign
AQ ALU Quotient
MV MAC Overflow
SS Shifter Input Sign
SSTAT (Read -Only)
7 6 5 4 32 10
01010101
PC Stack Empty
PC Stack Overflow
Count Stack Empty
Count Stack Overflow
Status Stack Empty
Status Stack Overflow
Loop Stack Empty
Loop Stack Overflow
MSTAT
6 5 4 32 10
0000000
Data Register Bank Select
0 = primary, 1 = secondary
Bit Reverse Mode Enable (DAG1)
ALU Overflow Latch Mode Enable
AR Saturation Mode Enable
MAC Result Placement
0 = fractional, 1 = integer
Timer Enable
Go Mode Enable
System Control Register
0x3FFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000010000111111
SPORT0 Enable
1 = enabled, 0 = disabled
SPORT1 Enable
1 = enabled, 0 = disabled
SPORT1 Configure
1 = serial port
0 = FI, FO, IRQ0, IRQ1, SCLK
BFORCE
Boot Force Bit
PWAIT
Program Memory
BWAIT
Wait States
Boot Wait States
BPAGE
Boot Page Select
Timer Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPERIOD Period Register
0x3FFD
TCOUNT Counter Register
0x3FFC
00000000
TCOUNT Scaling Register
0x3FFB
Control Registers
–12–
REV. 0

12 Page





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