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WM8501 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8501
Beschreibung 24-bit 192kHz Stereo DAC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 21 Seiten
WM8501 Datasheet, Funktion
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WM8501
24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver
DESCRIPTION
The WM8501 is a high performance stereo DAC with an
integrated 1.7Vrms line driver. It is designed for audio
applications that require a high voltage output along with
enhanced load drive capability.
The WM8501 supports data input word lengths from 16 to
24-bits and sampling rates up to 192kHz. The WM8501
consists of a serial interface port, digital interpolation filters,
multi-bit sigma delta modulators and stereo DAC in a 14-
lead SOIC package.
The hardware control interface is used for the selection of
audio data interface format, enable and de-emphasis. The
WM8501 supports I2S, right Justified or DSP interfaces.
Operating on separate analog and digital supplies the
WM8501 offers very lower power consumption from the
digital section, whilst supporting enhanced load drive from
the analogue output.
FEATURES
Stereo DAC with 1.7Vrms line driver from 5V analogue
supply
Audio performance
- 100dB SNR (‘A’ weighted @ 48kHz)
- -88dB THD
DAC Sampling Frequency: 8kHz – 192kHz
Pin Selectable Audio Data Interface Format
- I2S, 16-bit Right Justified or DSP
14-lead SOIC package
4.5V - 5.5V analogue, 2.7V - 5.5V digital supply operation
APPLICATIONS
STB
DVD
Digital TV
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, February 2013, Rev 4.3
Copyright 2013 Wolfson Microelectronics plc






WM8501 Datasheet, Funktion
WM8501
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
0.8
Input HIGH level
VIH
2.0
Output LOW
Output HIGH
Analogue Reference Levels
VOL
VOH
IOL = 2mA
IOH = 2mA
DVDD – 0.3V
DGND + 0.3V
Reference voltage (VMID)
AVDD/2
Potential divider resistance
RCAP
AVDD to VMID and
VMID to GND
50
DAC Output (Load = 10k. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.6 x
AVDD/5
1.7 x
AVDD/5
1.8 x
AVDD/5
Signal to Noise Ratio (Note
5,6,7)
SNR
A-weighted,
90 100
@ fs = 48kHz
A-weighted
97
@ fs = 96kHz
A-weighted
97
@ fs = 192kHz
Dynamic Range (Note 2, 6)
DNR
A-weighted, -60dB full
scale input
90
100
Total Harmonic Distortion
(Note 7)
THD
1kHz, Load = 10k,
0dBFS
-88 -78
DAC channel separation
93
Analogue Output Levels
Output level (line output)
Load = 10k, 0dBFS
1.7
Minimum resistance load (line
output)
To midrail or a.c.
coupled
820
Output level (Headphone output)
Load = 16, 0dBFS
1.0
Minimum resistance load
(Headphone output)
To midrail or a.c.
coupled
16
Gain mismatch
channel-to-channel
±1
Output d.c. level
AVDD/2
Supply Current
Analogue supply current
AVDD = 5V
9
Digital supply current
DVDD = 5V
8
DVDD = 3.3V
4.5
Power down current (note 4)
AVDD=DVDD=5V
0.01
UNIT
V
V
V
V
V
k
Vrms
dB
dB
dB
dB
dB
dB
Vrms
Vrms
%FSR
V
mA
mA
mA
mA
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics.
The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
3. VMID pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. Power down occurs 1.5s after MCLK is stopped.
5. Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output with no
signal applied. (No Auto-zero or Automute function is employed in achieving these results).
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PD, Rev 4.3, February 2013
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WM8501 pdf, datenblatt
WM8501
Production Data
LRCLK
BCLK
DIN
Max 4 BCLK's
1/f
LEFT CHANNEL
RIGHT CHANNEL
12
MSB
11
1
LSB
2
Input Word Length (16 bits)
1 16
NO VALID DATA
1
Figure 6 DSP Mode B Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8501 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8501 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCLK, although the WM8501 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
(LRCLK)
128fs
MASTER CLOCK FREQUENCY (MHz) (MCLK)
192fs
256fs
384fs
512fs
32kHz
4.096
6.144
8.192
12.288
16.384
44.1kHz
5.6448
8.467
11.2896
16.9344
22.5792
48kHz
6.144
9.216
12.288
18.432
24.576
96kHz
12.288
18.432
24.576
36.864 Unavailable
192kHz
24.576
36.864 Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
768fs
24.576
33.8688
36.864
Unavailable
Unavailable
HARDWARE CONTROL MODES
The WM8501 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
ENABLE OPERATION
Pin 4 (ENABLE) controls the operation of the chip. If ENABLE is low the device is held in a low
power state. If this pin is held high the device is powered up.
To ensure correct operation it is essential that there is a low to high transition on the ENABLE pin
after digital supplies have come on. This can be achieved by providing the ENABLE signal from
an external controller chip or by means of a simple RC network on the ENABLE pin. See
“Recommended External Components” in the “Application Information” section at the end of this
datasheet.
Note that the ENABLE pin should not be used as a mute pin or to temporarily silence the DAC
(between tracks of a CD for example). The ENABLE pin is not intended to be used as a mute
control but to allow entry into low power mode. Disabling the device via the ENABLE pin has the
effect of powering down the voltage on the VMID pin. Repeated enabling/disabling of the device
can cause audible pops at the output.
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PD, Rev 4.3, February 2013
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