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PDF CD2481 Data sheet ( Hoja de datos )
| Número de pieza | CD2481 | |
| Descripción | Programmable 4-Channel Communications Controller | |
| Fabricantes | Intel | |
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CD2481
Programmable Four-Channel Communications Controller
Datasheet
The CD2481 is a four-channel synchronous/asynchronous communications controller
specifically designed to reduce host-system processing overhead and increase efficiency in a
wide variety of communications applications. A special member of the CD24X1 family, the
device allows easy field upgrades and enhancement with an on-chip 8K-word microcode store
for downloaded control code. The CD2481 is packaged in a 100-pin MQFP package that offers
10 data/clock/modem pins per channel. The device has four fully independent serial channels to
support standard asynchronous, PPP, MNP4, SLIP, bit-synchronous (HDLC), and byte-
synchronous (bisync, X.21) protocols. The device is non-functional until the microcode is
downloaded; only a small boot ROM with code to perform device initialization is included.
The device is based on a proprietary on-chip RISC processor that performs all the time-critical,
low-level tasks otherwise performed by the host system.
The CD2481 boosts system efficiency with eight on-chip DMA channels, on-chip FIFOs (16
bytes/direction), intelligent vectored interrupts, and intelligent protocol processing. The on-chip
DMA controller provides ‘fire-and-forget’ transmit support — the host need only inform the
CD2481 of the location of the packet to send. Similarly, on receive, the CD2481 automatically
receives a complete packet with no host intervention or assistance. The DMA controller also has
a transmit ‘Append mode’ for use in asynchronous applications.
The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer
schemes. Each channel and direction in the dual-buffer scheme has two active buffers.
The CD2481 can be programmed to interrupt the host at the completion of a frame or buffer. In
applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames
to be divided into multiple buffers.
For applications where a DMA interface is not desired, the device can be operated as either
interrupt-driven or polled. This choice is available for each channel and each direction. For
example, a channel can be programmed for DMA transmit and interrupt-driven receive. In either
case, 16-byte FIFOs on each channel and in each direction reduce latency time requirements,
making both software and hardware designs less time-critical. Threshold levels on the FIFOs are
user-programmable.
Vectored interrupts are another way the CD2481 helps system efficiency. Separate interrupts are
generated for transmit, receive, and modem-signal/timer changes with unique, user-defined
vectors for each type and channel. This allows very flexible interfacing and fast, efficient
interrupt coding. For example, the Good Data interrupt allows the host to vector directly to a
routine that transfers the receive data — no status or error checking is required.
As of May 2001, this document replaces the Basis Communications Corp.
document CL-CD2481 — Programmable Four-Channel Communications Controller.
May 2001
1 page  
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Programmable Four-Channel Communications Controller — CD2481
7.6.3 CRC Calculation in Bisync Mode ...........................................................93
7.6.4 BCC Computation Formulas ..................................................................94
7.6.5 Receive State Tables .............................................................................95
7.7 X.21 Call Set-Up Mode........................................................................................97
7.7.1 X.21 Transmit .........................................................................................97
7.7.2 X.21 Receive ..........................................................................................97
7.8 Extended X.21 Mode...........................................................................................99
7.8.1 Extended X.21 Transmit.........................................................................99
7.8.2 Extended X.21 Receive..........................................................................99
7.9 Programmable Sync..........................................................................................100
7.9.1 Programmable Sync Transmit..............................................................101
7.9.2 Programmable Sync Receive...............................................................101
7.10 Non-8-Bit Data Transfers ..................................................................................102
8.0 Programming Examples ......................................................................................103
8.1 Global Initialization ............................................................................................105
8.2 Async Interrupt Setup Example.........................................................................107
8.3 HDLC DMA Channel Setup Example................................................................107
8.4 Receive DMA Interrupt Service Routine............................................................109
8.5 Transmit Interrupt Service Routine....................................................................110
8.6 Support Files from the Intel FTP Server............................................................110
9.0 Detailed Register Descriptions ........................................................................112
9.1 Global Registers................................................................................................112
9.1.1 Global Firmware Revision Code Register (GFRCR) ............................112
9.1.2 Channel Access Register (CAR) ..........................................................112
9.2 Option Registers................................................................................................113
9.2.1 Channel Mode Register (CMR) ............................................................113
9.2.2 Channel Option Register 1 (COR1)......................................................114
9.2.3 Channel Option Register 2 (COR2)......................................................116
9.2.4 Channel Option Register 3 (COR3)......................................................123
9.2.5 Channel Option Register 4 (COR4)......................................................130
9.2.6 Channel Option Register 5 (COR5)......................................................131
9.2.7 Channel Option Register 6 (COR6)......................................................132
9.2.8 Channel Option Register 7 (COR7)......................................................135
9.2.9 Special Character Registers –
Async and Programmable Sync Modes136
9.2.10 Special Character Range – Async Mode Only .....................................138
9.2.11 LNext Character (LNXT) – Async Mode Only ......................................139
9.2.12 Receive Frame Address Registers – HDLC Sync Mode Only .............139
9.2.13 CRC Polynomial Select Register (CPSR) ............................................141
9.2.14 Transmit Special Mapped Characters – PPP Mode only .....................141
9.2.15 Transmit Async Control Character Maps –
Async-HDLC/PPP Mode Only142
9.2.16 Receive Async Control Character Maps –
Async-HDLC/PPP Mode Only143
9.3 Bit Rate and Clock Option Registers.................................................................145
9.3.1 Receive Baud Rate Generator Registers .............................................145
9.3.2 Transmit Baud Rate Generator Registers ............................................146
9.4 Channel Command and Status Registers .........................................................148
9.4.1 Channel Command Register (CCR) .....................................................148
Datasheet
5
5 Page 
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Programmable Four-Channel Communications Controller — CD2481
Other Features
• Improved interrupt schemes
— Vectored interrupts per channel allow direct jump into proper service routines
— Good Data interrupts eliminate need for status checks
• Easily cascaded for multiple-device configurations
• 16-byte receive and transmit FIFOs
• Programmable Big- or Little-endian orientation
• Ten data / clock / modem control signals per channel
Figure 1. Functional Block Diagram
HOST
INTERFACE
HOST BUS
INTERFACE
LOGIC
REGISTER
RAM
ON-CHIP DMA
CONTROLLER
AND
INTERFACE
LOGIC
MICROCODE
RAM
(8K WORDS)
BOOT
ROM
(256 WORDS)
PROPRIETARY
RISC
PROCESSOR
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
4 SERIAL
INTERFACE
CHANNELS
1.1 Benefits
• Substantially reduced host CPU overhead resulting in more channels and faster overall
throughput
• No time-critical host software enabling faster and easier software development
• Smallest possible footprint for multi-channel device
Datasheet
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