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PDF CY7C1473V33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1473V33 | |
| Descripción | (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1471V33
CY7C1473V33
CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description [1]
• No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V IO supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self timed writes
• Asynchronous Output Enable (OE)
• CY7C1471V33, CY7C1473V33 available in
JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475V33
available in Pb-free and non-Pb-free 209-Ball FBGA
package
• Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion
• Automatic power down feature available using ZZ mode or
CE deselect
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst Capability — linear or interleaved burst order
• Low standby power
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst
SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock
cycle.Maximum access delay from the clock rise is 6.5 ns
(133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
305
120
117 MHz
8.5
275
120
Unit
ns
mA
mA
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *J
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised July 04, 2007
1 page  
www.DataSheet4U.com
Pin Configurations (continued)
100-Pin TQFP Pinout
CY7C1471V33
CY7C1473V33
CY7C1475V33
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1473V33
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68 DQA
67
66
VSS
NC
BYTE A
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05288 Rev. *J
Page 5 of 32
5 Page 
www.DataSheet4U.com
CY7C1471V33
CY7C1473V33
CY7C1475V33
Truth Table
The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Address
Used
CE1
CE2 CE3
ZZ
ADV/LD
WE
BWX OE
CEN CLK
DQ
None H X X L
L
X X X L L->H Tri-State
None X X H L
L
X X X L L->H Tri-State
None X L X L
L
X X X L L->H Tri-State
None X X X L
H
X X X L L->H Tri-State
External L H L L
L
H X L L L->H Data Out (Q)
Next X X X L
H
X X L L L->H Data Out (Q)
External L H L L
L
H X H L L->H Tri-State
Next X X X L
H
X X H L L->H Tri-State
External L H L L
L
L L X L L->H Data In (D)
Next X X X L
H
X L X L L->H Data In (D)
None L H L L
L
L H X L L->H Tri-State
Next X X X L
H
X H X L L->H Tri-State
Current X X X L
None X X X H
X
X
X X X H L->H
-
X X X X X Tri-State
Notes
2.
X = “Don't Care.” H =
Selects are asserted,
Logic HIGH, L =
see “Truth Table
LfoorgRiceLaOd/WW.riBteW” Xon=pLasgiegn1i2fiefosradteletaaislst.one
Byte
Write
Select
is
active,
BWX
=
Valid
signifies
that
the
desired
Byte
Write
3. Write is defined by BWX, and WE. See “Truth Table for Read/Write” on page 12.
4. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
8.
OE is asynchronous and is not sampled with the
is inactive or when the device is deselected, and
clock rise. It is masked
DQs and DQPX = data
internally
when OE
during write
is active.
cycles.
During
a
read
cycle
DQs
and
DQPX
=
tri-state
when
OE
Document #: 38-05288 Rev. *J
Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1473V33.PDF ] | |
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