PDF DS25C400 Data sheet ( Hoja de datos )

Número de pieza	DS25C400
Descripción	Quad 2.5 Gbps Serializer/Deserializer
Fabricantes	National Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY September 2002 DS25C400 Quad 2.5 Gbps Serializer/Deserializer General Description The DS25C400 is a four-channel serializer/deserializer (SERDES) for high-speed serial data transmission over con- trolled impedance transmission media such as a printed circuit board backplane or twin-axial cable. It is capable of transmitting and receiving serial data of 2.125 - 2.5 Gbps or 1.0625 - 1.25 Gbps per channel. Each transmit section of the DS25C400 contains a low-jitter clock synthesizer, an 8-bit or 10-bit parallel to serial con- verter with built in 8b/10b encoder, and a CML output driver with selectable pre-emphasis optimized for backplane appli- cations. Its receive section contains an input limiting ampli- fier with on-chip terminations and selectable equalization levels, a clock/data recovery PLL, a comma detector and a serial to parallel converter with built-in 8b/10b decoder. The DS25C400 has built-in local loopback test mode, pseudo-random pattern generator and error detector to sup- port self-testing. The DS25C400 requires no external components for its clock synthesizers and clock recovery PLL’s. Three external resistors are needed to set the proper bias currents and compensate for process variations to achieve tight tolerance on-chip terminations. Features n Quad Serializer/Deserializer n Data rate per channel: 2.125 - 2.5 Gbps or 1.0625 - 1.25 Gbps n Supports 106.25 - 125 MHz differential reference input clock n Low jitter clock synthesizers for clock distribution n 8-bit or 10-bit parallel I/O Interface conforms to SSTL_18 Class 1 (also interfaces to 1.8V HSTL or 1.8V LVCMOS) n On-chip 8b/10b encoder and decoder n High speed serial CML drivers n High speed serial CML on-chip terminations n Selectable pre-emphasis and equalization n On-chip Comma Detect for character alignment n On-chip local loopback test mode n On-chip pattern generator and error checker to support BIST n Hot plug protection n Low power, 420 mW (typ) per channel n 324-ball TE-PBGA package n Operating temperature −40˚C to +85˚C General Function Diagram © 2002 National Semiconductor Corporation DS200301 20030101 www.national.com 1 page www.DataSheet4U.com Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Continued) Symbol Parameter Conditions SERIALIZER DRDO Transmit Data Rate Data Rate at DO± High Data Rate Mode (EN_HDR = 1) Low Data Rate Mode (EN_HDR = 0) VODS Output Differential Voltage DO+, DO− are terminated by external Swing (DO+ − DO−) WITHOUT 50Ω to VDDHS Pre-emphasis PSEL1 = 0, PSEL0 = 0 Output Differential Voltage DO+, DO− are terminated by external Swing (DO+ − DO−) WITH Pre-emphasis 50Ω to VDDHS PSEL1 = 0, PSEL0 = 1 PSEL1 = 1, PSEL0 = 0 PSEL1 = 1, PSEL0 = 1 VCM Output Common Mode Offset DO+, DO− are terminated by external Voltage WITHOUT 50Ω to VDDHS Pre-emphasis PSEL1 = 0, PSEL0 = 0 Output Common Mode Offset Voltage WITH Pre-emphasis DO+, DO− are terminated by external 50Ω to VDDHS PSEL1 = 0, PSEL0 = 1 PSEL1 = 1, PSEL0 = 0 Min 2.125 1.0625 850 TBD TBD TBD −10% −10% PSEL1 = 1, PSEL0 = 1 RDO Output Resistance CDO tDO-X JITDO-DJ JITDO-RJ JITDO-TJ tLAT-TX Capacitance to GND Serial Data Output Transition Time Serial Data Output Deterministic Jitter (Peak-to-Peak), (Notes 4, 5) Serial Data Output Random Jitter (Peak-to-Peak), (Notes 4, 5) Serial Data Output Total Jitter, (Notes 4, 5) Transmit Latency Figure 2 tDO-LOCK Lock Time DESERIALIZER DRRI Receive Data Rate VIDSRI RRI Differential Input Voltage Input Termination to VDDHS On-chip termination DO+ or DO− to VDDHS, RTERM = 249Ω DO+ or DO− to GND Measured between 20% and 80% of VODS Output K28.5 at 2.5 Gbps Output D21.5 at 2.5 Gbps Output K28.5 pattern at 2.5 Gbps at BER of 10−12 Transmit K28.5 from TD[0–9] to DO± at 2.5 Gbps, EN_10B = 1 Transmit K28.5 from TD[0–9] to DO± at 2.5 Gbps, EN_10B = 0 Time to achieve frequency lock to REFCLK. Output K28.5 at 2.5 Gbps. High Data Rate (EN_HDR = 1) Low Data Rate (EN_HDR = 0) RI+ – RI− On-chip termination RI+ to RI− to VDDHS EN_RAC = 0, RTERM = 249Ω: 45 100 35 45 2.125 1.0625 200 45 Typ (Note 2) 1065 1330 1600 1850 VDDHS −0.3 VDDHS −0.37 VDDHS −0.43 VDDHS −0.50 50 1 120 0.1 0.13 0.2 50 Max 2.5 1.25 1280 TBD TBD TBD +10% +10% 55 160 0.13 0.15 0.25 48 58 0.5 2.5 1.25 1500 55 Units Gbps Gbps mVp-p mVp-p V V Ω pF ps UI UI UI Bits Bits ms Gbps Gbps mVp-p Ω 5 www.national.com 5 Page www.DataSheet4U.com Termination at the High Speed Interface 20030111 FIGURE 8. High Speed Interface — Direct-Coupled Mode (EN_RAC = 0) 20030112 FIGURE 9. High Speed Interface — AC-Coupled Mode (EN_RAC = 1) 11 www.national.com 11 Page

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