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PCF5213CAF66 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer PCF5213CAF66
Beschreibung Microcontroller
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
PCF5213CAF66 Datasheet, Funktion
www.DataSheet4U.com
Freescale Semiconductor
Data Sheet
MCF5213EC
Rev. 0, 05/2005
MCF5213 Microcontroller Family
Hardware Specification
The MCF5213 is a member of the ColdFire® family of
reduced instruction set computing (RISC)
microprocessors. This hardware specification provides
an overview of the 32-bit MCF5213 microcontroller,
focusing on its highly integrated and diverse feature set.
Freescale reserves the right to change or discontinue this
product without notice. Specifications and information
herein are subject to change without notice.
This 32-bit device is based on the Version 2 ColdFire
core operating at a frequency up to 80 MHz, offering
high performance and low power consumption. On-chip
memories connected tightly to the processor core include
256 Kbytes of Flash and 32 Kbytes of static random
access memory (SRAM). On-chip modules include the
following:
• V2 ColdFire core delivering 76 MIPS
(Dhrystone 2.1) at 80 MHz running from
internal Flash with Multiply Accumulate (MAC)
Unit and hardware divider
• FlexCAN controller area network (CAN)
module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
Table of Contents
1 MCF5213 Family Configurations .........................2
1.1 Block Diagram ...................................................3
1.2 Features.............................................................4
1.3 Part Numbers and Packaging..........................14
1.4 Package Pinouts..............................................15
1.5 Reset Signals ..................................................20
1.6 PLL and Clock Signals ....................................20
1.7 Mode Selection................................................21
1.8 External Interrupt Signals ................................21
1.9 Queued Serial Peripheral Interface (QSPI) .....22
1.10 I2C I/O Signals.................................................22
1.11 UART Module Signals .....................................22
1.12 DMA Timer Signals..........................................23
1.15 Pulse Width Modulator Signals........................24
1.16 Debug Support Signals....................................24
1.17 EzPort Signal Descriptions ..............................26
1.18 Power and Ground Pins...................................26
2 Preliminary Electrical Characteristics................26
3 Mechanical Outline Drawings ............................42
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.






PCF5213CAF66 Datasheet, Funktion
www.DataSheet4U.com
MCF5213 Family Configurations
— No read/write semaphores
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for
MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— “Time stamp” based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
• Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
• I2C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
• Fast Analog-to-Digital Converter (ADC)
— Eight analog input channels
— 12-bit resolution ± 2.5 counts accuracy
— Minimum 2.25 µs conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over
low/high limit
— Unused analog channels can be used as digital I/O
MCF5213 Microcontroller Family Hardware Specification, Rev. 0
6 Freescale Semiconductor

6 Page









PCF5213CAF66 pdf, datenblatt
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MCF5213 Family Configurations
1.2.10 QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with
queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU
intervention between transfers.
1.2.11 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold
(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible
buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or
perform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for either sequential or simultaneous conversion. When configured for
sequential conversions, up to eight channels can be sampled and stored in any order specified by the
channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same
time. This configuration requires that a single channel may not be sampled by both S/H circuits
simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures
below the low threshold limit or above the high threshold limit set in the limit registers) or at several
different zero crossing conditions.
1.2.12 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)
on the MCF5213. Each module incorporates a 32-bit timer with a separate register set for configuration
and control. The timers can be configured to operate from the system clock or from an external clock
source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The
input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter
register (TCRn). Each of these timers can be configured for input capture or reference (output) compare
mode. Timer events may optionally cause interrupt requests or DMA transfers.
1.2.13 General Purpose Timer (GPT)
The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable
counter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input
capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse
accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit
range of the counter. The input capture and output compare functions allow simultaneous input waveform
measurements and output waveform generation. The input capture function can capture the time of a
MCF5213 Microcontroller Family Hardware Specification, Rev. 0
12 Freescale Semiconductor

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