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PDF RT9241A Data sheet ( Hoja de datos )
| Número de pieza | RT9241A | |
| Descripción | (RT9241A/B) 2-Phase DC/DC Controller | |
| Fabricantes | RichTek Technology | |
| Logotipo |  |
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RT9241A/B
Two-Phase DC/DC Controller for CPU Core Power Supply
General Description
The RT9241A/B is a two-phase buck DC/DC
controller integrated with all control functions for high
performance processor VRM. The RT9241A/B
drives 2 buck switching stages operating in 180
degree phase shift. The two-phase architecture
provides high output current while maintaining low
power dissipation on power devices and low stress
on input and output capacitors. The high equivalent
operating frequency also reduces the component
dimension and the output voltage ripple in load
transient.
RT9241A/B regulates both easily set voltage and
current loops. Precise current sharing for power stage
is achieved by differential input current sense and
processing circuit. The settings of current sense,
droop tuning and over current protection are
independent to compensation circuit of voltage loop.
The feature greatly facilitates the flexibility of CPU
power supply design and tuning.
The RT9241A/B uses a 5-bit DAC of 1.1V to 1.85V
(25mV/step) output with load current droop
compensation to meet the strict VRM transient
requirement. The IC monitors the VCORE voltage for
PGOOD and over voltage protection. Soft start, over
current protection and programmable under voltage
lockout are also provided to assure the safety of
microprocessor and power system.
Ordering Information
RT9241A/B
Package type
S : SOP-20
Operating temperature range
C: Commercial standard
Operating frequency version
A : 200KHz
B : 100KHz
Features
Two-Phase Power Conversion
VRM 9.0 DAC Output with Active Droop
Compensation for Fast Load Transient
Precise Channel Current Sharing with
Differential Sense Input
Hiccup Mode Over Current Protection
Programmable Under Voltage Lockout and Soft
Start
High Ripple Frequency, (Channel Frequency
Times Channel Number)
100KHz Version (RT9241B) for Lower Switching
Loss
Applications
Power Supply for Server and Workstation
Power Supply for High Current Microprocessor
Pin Configurations
Part Number
Pin Configurations
RT9241A/B CS
(Plastic SOP-20) VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
ADJ 8
DVD 9
SS 10
TOP VIEW
20 VDD
19 PGOOD
18 ISP1
17 PWM1
16 PWM2
15 ISP2
14 VSEN
13 GND
12 ISN1
11 ISN2
DS9241AB-01 October 2002
www.richtek.com
1
1 page  
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Typical Application Circuit
RT9241A/B
DS9241AB-01 October 2002
www.richtek.com
5
5 Page 
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The sensing circuit gets
feedback. RSP = RSN to
IXcIaLR=n×ScRPeSl
the
by
voltage
local
drop
caused by GM amplifier input bias current. IX is
sampled and held just before low side MOSFET turns
off (See Fig.2). Therefore,
IX(S / H)
=
IL(S / H) × RS
RSP
IL(S / H)
=
IL(AVG) −,
,
VO
L
×
TOFF
2
TOFF =
period =
VIN − VO
TSVIN
×
TS, for switching
IX(S / H)
=
IL(
AVG)
−
VO −
VIN − VO
VIN
2L
×
TS
×
RS
RSP
Falling Slope = VO /L IL
Inductor Current
IL (S/H)
IL (AVG)
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Fig. 2 Inductor Current and PWM Signal
Droop tuning
The S/H current signals from power channels are
injected to ADJ pin to create droop voltage.
VADJ
=
R ADJ
×
2
3
∑ IX
The DAC output voltage decreases by VADJ to form
the VCORE load droop(see Fig.3).
COMP
_
EA
VDAC
FB + _ VADJ
VDAC - VADJ
∑
∑ IX
ADJ
RADJ
Fig. 3 Droop Tune Circuit
2/3 IX1
2/3 IX2
RT9241A/B
Protection and SS function
For OVP, the RT9241A/B detects the VCORE by VSEN
pin. Eliminate the parasitic delay and noise influence
on the PCB path for fast and accurate detection. The
trip point of OVP is 120% of normal output level. The
PWM outputs are pulled low to turn on the low side
MOSFET and turn off the high side MOSFET of the
synchronous rectifier at OVP. The OVP latch can only
be reset by VDD or VDVD restart power on reset
sequence. The PGOOD detection trip point of VCORE
is ±8% out of the normal level. The PGOOD open
drain output pulls low when VOCRE exceeds the
range.
Soft start circuit generates a ramp voltage by charging
external capacitor with 10uA current after IC POR
acts. The PWM pulse width and VCORE are clamped
by the rising ramp to reduce the in-rush current and
protect the power components.
OCP is triggered if one channel S/H current signal IX>
75µA. Controller forces PWM output latched at high
impedance to turn off both high and low side
MOSFET in the power stage and initial the hiccup
mode protection. The SS pin voltage is pulled low with
a 10µA current after it is less than 90% VDD. The
converter restarts after SS pin voltage < 0.2V. Three
times of OCP disable the converter and only release
the latch by POR acts (see Fig.4).
COUNT = 1 COUNT = 2 COUNT = 3
4V
2V VCORE
SS
0V
IL
OVER LO AD
APPLIED
0A
T0T1
T2 T3T4
TIME
Fig. 4
DS9241AB-01 October 2002
www.richtek.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet RT9241A.PDF ] | |
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