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AD9781 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9781
Beschreibung 500 MSPS DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9781 Datasheet, Funktion
Data Sheet
FEATURES
High dynamic range, dual DAC parts
Low noise and intermodulation distortion
Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF
Innovative switching output stage permits usable outputs
beyond Nyquist frequency
LVDS inputs with dual-port or optional interleaved single-
port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS compliant, 72-lead LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
Dual 12-/14-/16-Bit,
LVDS Interface, 500 MSPS DACs
AD9780/AD9781/AD9783
GENERAL DESCRIPTION
The AD9780/AD9781/AD9783 include pin-compatible, high
dynamic range, dual digital-to-analog converters (DACs) with
12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.
The devices include specific features for direct conversion transmit
applications, including gain and offset compensation, and they
interface seamlessly with analog quadrature modulators such as
the ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. Some pin-programmable features are also
offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
CLKP
CLKN
LVDS
INTERFACE
D[15:0]
VIA, VIB
FUNCTIONAL BLOCK DIAGRAM
AD9783 DUAL LVDS DAC
INTERFACE LOGIC
SERIAL
PERIPHERAL
INTERFACE
INTERNAL
REFERENCE
AND
BIAS
GAIN
DAC
GAIN
DAC
OFFSET
DAC
OFFSET
DAC
16-BIT
I DAC
16-BIT
Q DAC
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.






AD9781 Datasheet, Funktion
AD9780/AD9781/AD9783
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD33, DVDD33
DVDD18, CVDD18
AGND
DGND
CGND
REFIO
IOUT1P, IOUT1N,
IOUT2P, IOUT2N,
AUX1P, AUX1N,
AUX2P, AUX2N
D15 to D0
CLKP, CLKN
CSB, SCLK, SDIO, SDO
Junction Temperature
Storage Temperature
With
Respect to
AGND, DGND, CGND
AGND, DGND, CGND
DGND, CGND
AGND, CGND
AGND, DGND
AGND
AGND
DGND
CGND
DGND
Rating
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to
AVDD33 + 0.3 V
−1.0 V to
AVDD33 + 0.3 V
−0.3 V to
DVDD33 + 0.3 V
−0.3 V to
CVDD18 + 0.3 V
–0.3 V to
DVDD33 + 0.3 V
+125°C
−65°C to +150°C
Data Sheet
THERMAL RESISTANCE
Thermal resistance is tested using a JEDEC standard 4-layer
thermal test board with no airflow.
Table 5.
Package Type
CP-72-1 (Exposed Pad Soldered to PCB)
θJA Unit
25 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 6 of 32

6 Page









AD9781 pdf, datenblatt
AD9780/AD9781/AD9783
90
85
80 250MSPS
75 400MSPS
70
65
60
55
500MSPS
50
45
40
0 50 100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 17. AD9783 SFDR vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA
100
95
90
85 20mA
80
75
30mA
70
65
60
55 10mA
50
45
40
0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz)
Figure 18. AD9783 SFDR vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
100
95
90
85
80 –3dBFS
75
70
65 –6dBFS
60 0dBFS
55
50
45
40
0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz)
Figure 19. AD9783 SFDR vs. fOUT Over Digital Input Level,
TA = 25°C, at 500 MSPS, FS = 20 mA
Data Sheet
100
95
90
85 +25°C
80
75
–40°C
70
65
+85°C
60
55
50
45
40
0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz)
Figure 20. AD9783 SFDR vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA
100
95
90
250MSPS
85
80
75
70
65 400MSPS
60
55
500MSPS
50
45
40
0 50 100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 21. AD9783 IMD vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA
100
95
90
85 10mA
80 20mA
75
70 30mA
65
60
55
50
45
40
0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz)
Figure 22. AD9783 IMD vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
Rev. B | Page 12 of 32

12 Page





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