Datenblatt-pdf.com


AD9782 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9782
Beschreibung 200 MSPS/500 MSPS TxDAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9782 Datasheet, Funktion
www.DataSheet4U.com
12-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
Preliminary Technical Data
AD9782
FEATURES
12-bit resolution, 200 MSPS input data rate
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
SFDR 90 dBc @10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.75 LSB
INL = ±1.5 LSB
3.3 V compatible digital Interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
APPLICATIONS
Digital quadrature modulation architectures
Multicarrier WCDMA, GSM, TDMA, DCS,
PCS, CDMA Systems
PRODUCT DESCRIPTION
The AD9782 is a 12-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for
communications applications. It offers state of the art distortion
and noise performance. The AD9782 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9782 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9782 is
manufactured on an advanced low cost 0.25 µm CMOS process.
P1B[15:0]
P2B[15:0]
DATACLK/
PLL_LOCK
FUNCTIONAL BLOCK DIAGRAM
LATCH
×1
LATCH
2× 2× 2×
I
fDAC/2
fDAC/4
fDAC/8
0
90
×2
×4
×8
Q
0
90
0
90
t
ZERO
STUFF
16-BIT DAC
HILBERT
FSADJ
REFIO
IOUTA
IOUTB
SDIO
SDO
CSB
SCLK
RESET
CLK+
CLK–
LPF
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD9782 Datasheet, Funktion
www.DataSheet4U.com
AD9782
Preliminary Technical Data
DIGITAL SPECIFICATIONS
Table 3. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless
otherwise noted
Parameter
Min Typ Max
DIGITAL INPUTS
Logic 1 Voltage
DRVDD – 0.9
DRVDD
Logic 0 Voltage
0 0.9
Logic 1 Current
–10
+10
Logic 0 Current
–10
+10
Input Capacitance
5
LOCK INPUTS
Input Voltage Range
0
2.65
Common-Mode Voltage
0.75 1.5 2.25
Differential Voltage
0.5 1.5
PLL CLOCK ENABLED
Input Setup Time (ts)
Input Hold Time (tH)
Latch Pulse Width (tLPW)
PLL CLOCK DISABLED
Input Setup Time (ts)
Input Hold Time (tH)
Latch Pulse Width (tLPW)
CLK to PLLLOCK Delay (tOD)
Unit
V
V
µA
µA
pF
V
V
V
ns
ns
ns
ns
ns
ns
ns
Rev. PrC | Page 6 of 52

6 Page









AD9782 pdf, datenblatt
www.DataSheet4U.com
AD9782
Preliminary Technical Data
TYPICAL PERFORMANCE CHARATCERISTICS
(TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, Differential Transformer
Coupled Output, 50 Ω Doubly Terminated, unless otherwise noted)
–000
–000
–000
TBD–000
–000
–000
TBD–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 3 Single-Tone Spectrum@ FDATA = 65 MSPS With FOUT = FDATA/3
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 6. Single-Tone Spectrum @ FDATA = 78 MSPS with FOUT = FDATA/3
–000
–000
TBD–000
–000
–000
TBD–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
Figure 4. In-Band SFDR vs. FOUT @ FDATA = 65 MSPS
–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
Figure 7. In-Band SFDR Vs. FOUT @ FDATA = 78 MSPS
–000
–000
–000
TBD–000
–000
–000
TBD–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 5. Out-of-Band SFDR vs. FOUT @ FDATA = 65 MSPS
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 8. Out-of-Band SFDR vs. FOUT @ FDATA = 78 MSPS
Rev. PrC | Page 12 of 52

12 Page





SeitenGesamt 30 Seiten
PDF Download[ AD9782 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD9780500 MSPS DACsAnalog Devices
Analog Devices
AD9781500 MSPS DACsAnalog Devices
Analog Devices
AD9782200 MSPS/500 MSPS TxDACAnalog Devices
Analog Devices
AD9783500 MSPS DACsAnalog Devices
Analog Devices
AD9784TxDACAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche