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PDF AD73522 Data sheet ( Hoja de datos )
| Número de pieza | AD73522 | |
| Descripción | Dual Analog Front End | |
| Fabricantes | Analog Devices | |
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a
Dual Analog Front End
with Flash based DSP Microcomputer
Preliminary Technical Data
AD73522
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AFE PERFORMANCE
Two 16-Bit A/D Converters
78 dB ADC SNR
Two 16-Bit D/A Converters
77 dB DAC SNR
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
16K PM
(OPTIONAL 8K)
16K DM
(OPTIONAL 8K)
Programmable Input/Output Sample Rates
64 kS/s Maximum Sample Rate
PROGRAM MEMORY ADDRESS
Programmable Input/Output Gain
DATA MEMORY ADDRESS
On-Chip Reference
DSP PERFORMANCE
Y19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
RSustained Performance
AAD73522-80
80K Bytes of On-Chip RAM, Configured as 16K Words
IN LProgram Memory RAM and 16K Words
Data Memory RAM
IM AAD73522-40
L IC40K Bytes of On-Chip RAM, Configured as 8K Words
Program Memory RAM and 8K Words
E NData Memory RAM
PR HFLASH Memory
C A64 kbytes
E TWritable in pages of 128 bytes
T DAFast Page Write Cycle of 5 ms (typical)
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
SERIAL PORT
REF
SPORT 2
ADC1
DAC1
ADC2
ANALOG FRONT END
SECTION
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
DAC2
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
FLASH
Byte Memory
64 kbytes
GENERAL DESCRIPTION
The AD73522 is a single-device incorporating a dual analog
front end, microcomputer optimized for digital signal
processing (DSP) and a FLASH based boot memory for the
DSP.
The AD73522’s analog front end (AFE) section features a
dual front-end converter for general purpose applications
including speech and telephony. The AFE section features
two 16-bit A/D conversion channels and two 16-bit D/A
conversion channels. Each channel provides 77 dB signal-to-
noise ratio over a voiceband signal bandwidth. It also features
an input to output gain network in both the analog and digital
domains. This is featured on both codecs and can be used for
impedance matching or scaling when interfacing to Subscriber
Line Interface Circuits (SLICs)
The AD73522 is particularly suitable for a variety of applica-
tions in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. The low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
applications. The A/D and D/A conversion channels feature
REV. PrC 05/99
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
programmable input/ouput gains with ranges 38 dB and 21
dB respectively. An on-chip reference voltage is included
to allow single supply operation.
The AD73522’s DSP engine combines the ADSP-2100
family base architecture (three computational units, data
address generators and a program sequencer) with two serial
ports, a 16-bit internal DMA port, a byte DMA port, a
programmable timer, Flag I/O, extensive interrupt capabilities
and on-chip program and data memory.
The AD73522-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73522-40 integrates
40K bytes of on-chip memory configured as 8K words (24-
bit) of program RAM, and 8K words (16-bit) of data RAM.
Both devices feature a Flash memory array of 64 kbytes (512
kbits) connected to the DSP’s byte-wide DMA port
(BDMA). This allows non-volatile storage of the DSP’s boot
code and system data parameters. Power-down circuitry is
also provided to meet the low power needs of battery
operated portable equipment. The AD73522 is available in a
119-ball PBGA package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
1 page  
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Preliminary Technical Data
AD73522
PARAMETER
Min Typ Max Units Test Conditions (STYLE: table col.head)
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single Ended
1.578
V p-p PGA = 6 dB
Differential
–2.85
3.156
dBm Max. Output = (1.578/1.2)*VREFCAP
V p-p PGA = 6 dB
Nominal Voltage Output Swing (0 dBm0)
3.17
dBm Max. Output = 2*((1.578/1.2)*VREFCAP)
Single-Ended
1.0954
V p-p PGA = 6 dB
–6.02
dBm
Differential
2.1909
V p-p PGA = 6 dB
0 dBm
Output Bias Voltage
1.2 V REFOUT Unloaded
Absolute Gain
–0.5 +0.4 +1.2 dB 1.0 kHz, 0 dBm0; Unloaded
Gain Tracking Error
± 0.1
dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) at 0 dBm0
PGA = 6 dB
YTotal Harmonic Distortion at 0 dBm0
RPGA = 6 dB
Intermodulation Distortion
AIdle Channel Noise
INCrosstalk, DAC-to-ADC
LIM ICALDAC-to-DAC
RE NPower Supply Rejection
P CH AGroup Delay4, 5
TE ATOutput DC Offset2, 7
DMinimum Load Resistance, RL2, 8
62.5 77
dB
-80 –62.5 dB
–85 dB
Refer to Figure 6: AVDD = 3.00V +/- 5%
300 Hz to 3400 Hz; fSAMP = 64 kHz
AVDD = 3.00V +/- 5%
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
–85 dBm0 PGA = 0 dB
–90 dB ADC Input Level: AGND;
DAC Output Level: 1.0 kHz, 0 dBm0;
Input Amplifiers bypassed
-77 dB Input amplifiers included in input channel
–100
dB DAC1Output Level:AGND;
DAC2 Output Level: 1.0 kHz, 0 dBm0
–65 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
25 µs Interpolator Bypassed
50 µs
–20 +12 +45 mV
Single-Ended4
150 W
Differential
150 W
Maximum Load Capacitance, CL2, 8
Single-Ended4
500 pF
Differential
100 pF
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
DVDD – 0.8
0
-10
DVDD – 0.4
0
–10
DVDD
0.8
+10
10
V
V
µA
pF
DVDD
0.4
+10
V
V
µA
|IOUT| - 100 µA
|IOUT| - 100 µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
IDD10
3.0 3.6 V
3.0 3.6 V
See Table I
NOTES
1 Operating temperature range is as follows: –20°C to +85°C. Therefore, TMIN = –20°C and TMAX = +85°C.
2 Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3 At input to sigma-delta modulator of ADC.
4 Guaranteed by design.
5 Overall group delay will be affected by the sample rate and the external digital filtering.
6 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 ∗ 1011)/DMCLK.
7 Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
8 At VOUT output.
9 Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10 Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
REV. PrC 05/99
–5–
5 Page 
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Preliminary Technical Data
IRQ2/
PF7
IRQL0/
PF6
IRQL1/
PF5
IRQE/
PF4
Mode D/
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI
FO
PWD
PWDACK
FL0, FL1,
FL2
VDD and
GND
EZ-Port
(Input) Edge- or Level-Sensitive Interrupt
(Input/Output) Request.1 Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests1
(Input/Output) Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests1
(Input/Output) Programmable I/O Pin
(Input) Edge-Sensitive Interrupt Requests1
(Input/Output) Programmable I/O Pin
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Inputs) Clock or Quartz Crystal Input
Y(Output) Processor Clock Output
R(Inputs/Outputs) Serial Port I/O Pins
(Inputs/Outputs) Serial Port I/O Pins
A(Inputs) Edge- or Level-Sensitive Interrupts,
IN(Input) Flag In2
L(Output) Flag Out2
IM A(Input) Power-Down Control Input
L IC(Output) Power-Down Control Output
E N(Outputs) Output Flags
PR CH APower and Ground
TE DAT(Inputs/Outputs) For Emulation Use
AD73522
REV. PrC 05/99
–11–
11 Page | ||
| Páginas | Total 46 Páginas | |
| PDF Descargar | [ Datasheet AD73522.PDF ] | |
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