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EP2C5Q208C7 Schematic ( PDF Datasheet ) - Altera

Teilenummer EP2C5Q208C7
Beschreibung Cyclon II Device
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EP2C5Q208C7 Datasheet, Funktion
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Cyclone II Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
CII5V1-3.1






EP2C5Q208C7 Datasheet, Funktion
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VCCA & GNDA ............................................................................................................................. 7–30
VCCD & GND ................................................................................................................................. 7–33
Conclusion ............................................................................................................................................ 7–33
Section III. Memory
Revision History .................................................................................................................................... 7–1
Chapter 8. Cyclone II Memory Blocks
Introduction ............................................................................................................................................ 8–1
Overview ................................................................................................................................................. 8–1
Control Signals .................................................................................................................................. 8–3
Parity Bit Support ............................................................................................................................. 8–4
Byte Enable Support ........................................................................................................................ 8–4
Packed Mode Support ..................................................................................................................... 8–6
Address Clock Enable ...................................................................................................................... 8–6
Memory Modes ...................................................................................................................................... 8–8
Single-Port Mode .............................................................................................................................. 8–9
Simple Dual-Port Mode ................................................................................................................. 8–10
True Dual-Port Mode ..................................................................................................................... 8–12
Shift Register Mode ........................................................................................................................ 8–14
ROM Mode ...................................................................................................................................... 8–16
FIFO Buffer Mode ........................................................................................................................... 8–16
Clock Modes ......................................................................................................................................... 8–16
Independent Clock Mode .............................................................................................................. 8–17
Input/Output Clock Mode ........................................................................................................... 8–19
Read/Write Clock Mode ............................................................................................................... 8–22
Single-Clock Mode ......................................................................................................................... 8–24
Power-Up Conditions & Memory Initialization ........................................................................ 8–27
Read-During- Write Operation at the Same Address .................................................................... 8–28
Same-Port Read-During-Write Mode .......................................................................................... 8–28
Mixed-Port Read-During-Write Mode ........................................................................................ 8–29
Conclusion ............................................................................................................................................ 8–30
Chapter 9. External Memory Interfaces
Introduction ............................................................................................................................................ 9–1
External Memory Interface Standards ................................................................................................ 9–2
DDR & DDR2 SDRAM .................................................................................................................... 9–2
QDRII SRAM ..................................................................................................................................... 9–5
Cyclone II DDR Memory Support Overview .................................................................................... 9–9
Data & Data Strobe Pins ................................................................................................................ 9–10
Clock, Command & Address Pins ............................................................................................... 9–14
Parity, DM & ECC Pins ................................................................................................................. 9–14
Phase Lock Loop (PLL) .................................................................................................................. 9–15
Clock Delay Control ....................................................................................................................... 9–15
DQS Postamble ............................................................................................................................... 9–16
vi
Cyclone II Device Handbook, Volume 1
Altera Corporation

6 Page









EP2C5Q208C7 pdf, datenblatt
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Cyclone II Device Handbook, Volume 1
Chapter 10. Selectable I/O Standards in Cyclone II Devices
Revised:
February 2007
Part number: CII51010-2.3
Chapter 11. High-Speed Differential Interfaces in Cyclone II Devices
Revised:
February 2007
Part number: CII51011-2.2
Chapter 12. Embedded Multipliers in Cyclone II Devices
Revised:
February 2007
Part number: CII51012-1.2
Chapter 13. Configuring Cyclone II Devices
Revised:
February 2007
Part number: CII51013-3.1
Chapter 14. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
Revised:
February 2007
Part number: CII51014-2.1
Chapter 15. Package Information for Cyclone II Devices
Revised:
February 2007
Part number: CII51015-2.3
xii Altera Corporation

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