89HPES6T5 Datasheet PDF ( Pinout ) - 6-Lane 5-Port PCI Express Switch

89HPES6T5 Datasheet PDF - IDT

Part Number	*89HPES6T5*
Description	6-Lane 5-Port PCI Express Switch
Manufacturers	IDT
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6-Lane 5-Port

PCI Express® Switch

89HPES6T5

Data Sheet

Advance Information*

Device Overview

The 89HPES6T5 is a member of IDT’s PRECISE™ family of PCI

Express switching solutions. The PES6T5 is an 6-lane, 5-port peripheral

chip that performs PCI Express Base switching. It provides connectivity

and switching functions between a PCI Express upstream port and up to

four downstream ports and supports switching between downstream

ports.

Features

◆ High Performance PCI Express Switch

– Six 2.5Gbps PCI Express lanes

– Five switch ports

– Upstream port is x2

– Downstream ports are x1

– Low-latency cut-through switch architecture

– Support for Max Payload Sizes up to 256 bytes

– One virtual channel

– Eight traffic classes

– PCI Express Base Specification Revision 1.1 compliant

◆ Flexible Architecture with Numerous Configuration Options

– Automatic lane reversal on all ports

– Automatic polarity inversion

– Ability to load device configuration from serial EEPROM

◆ Legacy Support

– PCI compatible INTx emulation

– Bus locking

◆ Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates six 2.5 Gbps embedded SerDes with 8B/10B

encoder/decoder (no separate transceivers needed)

◆ Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports ECRC and Advanced Error Reporting

– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O

– Compatible with Hot-Plug I/O expanders used on PC mother-

boards

◆ Power Management

– Utilizes advanced low-power design techniques to achieve low

typical power consumption

– Support PCI Power Management Interface specification (PCI-

PM 1.2)

– Unused SerDes are disabled.

– Supports Advanced Configuration and Power Interface Speci-

fication, Revision 2.0 (ACPI) supporting active link state

◆ Testability and Debug Features

– Built in Pseudo-Random Bit Stream (PRBS) generator

– Numerous SerDes test modes

– Ability to read and write any internal register via the SMBus

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters

Block Diagram

Frame Buffer

5-Port Switch Core / 6 PCI Express Lanes

Route Table

Port

Arbitration

Scheduler

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

SerDes

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

SerDes

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

SerDes

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

SerDes

(Port 0)

(Port 2)

(Port 3)

(Port 4)

Figure 1 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 28

*Notice: The information in this document is subject to change without notice

(Port 5)

September 7, 2007

IDT 89HPES6T5 Data Sheet

Signal

Type

Name/Description

MSMBADDR[4:1]

I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK

I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT

I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK

I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT

I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 3 SMBus Interface Pins

Signal

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

Type

Name/Description

I/O General Purpose I/O.