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89HPES64H16 Schematic ( PDF Datasheet ) - IDT

Teilenummer 89HPES64H16
Beschreibung 64-Lane 16-Port PCI Express System Interconnect Switch
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
89HPES64H16 Datasheet, Funktion
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64-Lane 16-Port PCI Express®
System Interconnect Switch
®
89HPES64H16
Data Sheet
Device Overview
The 89HPES64H16 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES64H16 is a 64-lane, 16-port
system interconnect switch optimized for PCI Express packet switching
in high-performance applications, supporting multiple simultaneous
peer-to-peer traffic flows. Target applications include servers, storage,
communications, and embedded systems.
Features
High Performance PCI Express Switch
– Sixteen maximum switch ports
Eight main ports each of which consists of 8 SerDes
Each x8 main port can further bifurcate to 2 x4-ports
– Sixty-four 2.5 Gbps embedded SerDes
Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 256 Gbps (32 GBps) of aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Virtual channels arbitration based on priority
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates sixty-four 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Supports optional PCI Express end-to-end CRC checking
Block Diagram
x8/x4/x2/x1
SerDes
DL/Transaction Layer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Route Table
Frame Buffer
16-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
64 PCI Express Lanes
Up to 8 x8 ports or 16 x4 Ports
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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89HPES64H16 Datasheet, Funktion
IDT 89HPES64H16 Data Sheet
Signal
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Type
Name/Description
I Master SMBus Address. These pins determine the SMBus address of the serial
EEPROM from which configuration information is loaded.
I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
I Slave SMBus Address. These pins determine the SMBus address to which the slave
SMBus interface responds.
I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the
slave SMBus.
I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.
Table 3 SMBus Interface Pins
Signal
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
Type
Name/Description
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
Table 4 General Purpose I/O Pins (Part 1 of 4)
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89HPES64H16 pdf, datenblatt
IDT 89HPES64H16 Data Sheet
Pin Characteristics
Note: Some input pads of the PES64H16 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
PCI Express Interface
Pin Name Type Buffer
I/O Internal
Type Resistor
PE0RN[3:0] I CML Serial Link
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE1RN[3:0]
I
PE1RP[3:0]
I
PE1TN[3:0]
O
PE1TP[3:0]
O
PE2RN[3:0]
I
PE2RP[3:0]
I
PE2TN[3:0]
O
PE2TP[3:0]
O
PE3RN[3:0]
I
PE3RP[3:0]
I
PE3TN[3:0]
O
PE3TP[3:0]
O
PE4RN[3:0]
I
PE4RP[3:0]
I
PE4TN[3:0]
O
PE4TP[3:0]
O
PE5RN[3:0]
I
PE5RP[3:0]
I
PE5TN[3:0]
O
PE5TP[3:0]
O
PE6RN[3:0]
I
PE6RP[3:0]
I
PE6TN[3:0]
O
PE6TP[3:0]
O
PE7RN[3:0]
I
PE7RP[3:0]
I
PE7TN[3:0]
O
PE7TP[3:0]
O
PE8RN[3:0]
I
Table 8 Pin Characteristics (Part 1 of 3)
Notes
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