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PDF 89HPES4T4 Data sheet ( Hoja de datos )
| Número de pieza | 89HPES4T4 | |
| Descripción | 4-Lane 4-Port PCI Express Switch | |
| Fabricantes | IDT | |
| Logotipo |  |
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4-Lane 4-Port
PCI Express® Switch
®
89HPES4T4
Data Sheet
Advance Information*
Device Overview
The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
Features
◆ High Performance PCI Express Switch
– Four 2.5 Gbps PCI Express lanes
– Four switch ports
– x1 Upstream port
– Three x1 Downstream ports
– Low latency cut-through switch architecture
– Support for Max payload sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆ Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆ Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates four 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆ Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
◆ Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆ Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
Frame Buffer
4-Port Switch Core / 4 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
© 2007 Integrated Device Technology, Inc.
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 23
*Notice: The information in this document is subject to change without notice
(Port 4)
September 7, 2007
1 page  
IDT 89HPES4T4 Data Sheet
Signal
RSTHALT
SWMODE[2:0]
WAKEN
Type
Name/Description
I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES4T4 executes the reset procedure and remains in a reset
state with the Master SMBus active. This allows software to read and write
registers internal to the device before normal device operation begins. The
device exits the reset state when the RSTHALT bit is cleared in the
PA_SWCTL register by the SMBus master.
I Switch Mode. These configuration pins determine the PES4T4 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through WAKEDIR bit setting in
the WAKEUPCNTL register.
Table 4 System Pins (Part 2 of 2)
Signal
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
Type
Name/Description
I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 5 Test Pins
Signal
VDDCORE
VDDI/O
VDDPE
VDDAPE
VTTPE
VSS
Type
Name/Description
I Core VDD. Power supply for core logic.
I I/O VDD. LVTTL I/O buffer power supply.
I PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
I PCI Express Termination Power.
I Ground.
Table 6 Power and Ground Pins
5 of 23
September 7, 2007
5 Page 
IDT 89HPES4T4 Data Sheet
Recommended Operating Supply Voltages
Symbol
VDDCORE
VDDI/O
VDDPE
VDDAPE
VTTPE
VSS
Parameter
Minimum Typical
Internal logic supply
I/O supply except for SerDes LVPECL/CML
PCI Express Digital Power
PCI Express Analog Power
PCI Express Serial Data Transmit
Termination Voltage
Common ground
0.9
3.135
0.9
0.9
1.425
0
1.0
3.3
1.0
1.0
1.5
0
Table 12 PES4T4 Operating Voltages
Maximum
1.1
3.465
1.1
1.1
1.575
0
Unit
V
V
V
V
V
V
Power-Up/Power-Down Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES4T4, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels.
The power-down sequence must be in the reverse order of the power-up sequence.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Table 13 PES4T4 Operating Temperatures
11 of 23
September 7, 2007
11 Page | ||
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