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89HPES32H8 Schematic ( PDF Datasheet ) - IDT

Teilenummer 89HPES32H8
Beschreibung 32-Lane 8-Port PCI Express System Interconnect Switch
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
89HPES32H8 Datasheet, Funktion
www.DataSheet4U.com
32-Lane 8-Port PCI Express®
System Interconnect Switch
®
89HPES32H8
Data Sheet
Device Overview
The 89HPES32H8 is a member of the IDT PRECISE™ family of PCI
Express® switching solutions. The PES32H8 is a 32-lane, 8-port system
interconnect switch optimized for PCI Express packet switching in high-
performance applications, supporting multiple simultaneous peer-to-
peer traffic flows. Target applications include servers, storage, communi-
cations, and embedded systems.
Features
High Performance PCI Express Switch
– Eight maximum switch ports
Four main ports each of which consists of eight SerDes
Each x8 main port can further bifurcate to 2 x4-ports
– Thirty-two 2.5 Gbps embedded SerDes
Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 128 Gbps (16 GBps) aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Virtual channels arbitration based on priority
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all ports
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Block Diagram
x8/x4/x2/x1
SerDes
DL/Transaction Layer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Route Table
Frame Buffer
8-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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89HPES32H8 Datasheet, Funktion
IDT 89HPES32H8 Data Sheet
Signal
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
Type
Name/Description
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P7RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 7
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins (Part 2 of 3)
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89HPES32H8 pdf, datenblatt
IDT 89HPES32H8 Data Sheet
Logic Diagram — PES32H8
Reference
Clocks
PEREFCLKP[3:0]
PEREFCLKN[3:0]
REFCLKM
4
4
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 1
PCI Express
Switch
SerDes Input
Port 2
PCI Express
Switch
SerDes Input
Port 3
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PE1RP[0]
PE1RN[0]
PE1RP[3]
PE1RN[3]
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PE3RP[0]
PE3RN[0]
PE3RP[3]
PE3RN[3]
PCI Express
Switch
SerDes Input
Port 7
PE7RP[0]
PE7RN[0]
PE7RP[3]
PE7RN[3]
Master
SMBus Interface
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
System
Functions
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
4
PES32H8
PE0TP[0]
PE0TN[0]
PE0TP[3]
PE0TN[3]
PE1TP[0]
PE1TN[0]
PE1TP[3]
PE1TN[3]
PE2TP[0]
PE2TN[0]
PE2TP[3]
PE2TN[3]
PE3TP[0]
PE3TN[0]
PE3TP[3]
PE3TN[3]
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 1
PCI Express
Switch
SerDes Output
Port 2
PCI Express
Switch
SerDes Output
Port 3
PE7TP[0]
PE7TN[0]
PE7TP[3]
PE7TN[3]
PCI Express
Switch
SerDes Output
Port 7
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Slave
SMBus Interface
32 GPIO[31:0]
General Purpose
I/O
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG
VDDCORE
VDDIO
VDDPE
VDDAPE
VSS
VTTPE
Power/Ground
Figure 4 PES32H8 Logic Diagram
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