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PDF 89HPES24T6 Data sheet ( Hoja de datos )
| Número de pieza | 89HPES24T6 | |
| Descripción | 24-Lane 6-Port PCI Express Switch | |
| Fabricantes | IDT | |
| Logotipo |  |
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24-Lane 6-Port
PCI Express® Switch
89HPES24T6
Product Brief
Device Overview
The 89HPES24T6 is a member of the IDT PRECISE™ family of PCI
Express® switching solutions. The PES24T6 is a 24-lane, 6-port periph-
eral chip that performs PCI Express Packet switching with a feature set
optimized for high performance applications such as servers, storage,
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstream port and up to five down-
stream ports and supports switching between downstream ports.
Features
◆ High Performance PCI Express Switch
– Twenty-four 2.5 Gbps PCI Express lanes
– Six switch ports
– Upstream port configurable up to x8
– Downstream ports configurable up to x8
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆ Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆ Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/
10B encoder/decoder (no separate transceivers needed)
◆ Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
◆ Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
– Unused SerDes are disabled
Block Diagram
Frame Buffer
6-Port Switch Core / 24 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
(Port 0)
© 2007 Integrated Device Technology, Inc.
(Port 1)
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 2
(Port 5)
February 8, 2007
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet 89HPES24T6.PDF ] | |
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