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W83194BR-911 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194BR-911
Beschreibung STEPLESS VIA PT/PM MAIN CLOCK GENERATOR
Hersteller Winbond
Logo Winbond Logo 




Gesamt 25 Seiten
W83194BR-911 Datasheet, Funktion
www.DataSheet4U.com
W83194BR-911
W83194BG-911
Winbond STEPLESS VIA PT/PM
MAIN CLOCK GENERATOR
Date: Mar/22/2006
Revision: 0.71






W83194BR-911 Datasheet, Funktion
W83194BR-911, W83194BG-911
STEPLESS CLOCK FOR VIA PT/PM CHIPSET
3. PIN CONFIGURATION
FS1* /REF0
FS0 &/REF1
REF2
VDDREF
XIN
XOUT
GND
FS2 &/PCI_F0
FS4 &/PCI_F1
PCI_F2
VDDPCI
GND
MODE &/PCI0
PCI1
PCI2
PCI3
PCI4
VDDPCI
GND
PCI_STOP#* /PCI5
CPU_STOP#* /PCI6
VDDPCI
FS3 &/48MHz
SEL24_48# &/24_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDA
47 GND
46 IREF
45 RESET#
44 GND
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPU
40 CPUCLKT0
39 CPUCLKC0
38 GND
37 25MHz_0
36 25MHz_1
35 VDD2.5
34 VTT_PWRGD/PD#*
33 SDATA*
32 SCLK*
31 AGP_0
30 AGP_1
29 GND
28 VDDAGP
27 AGP_2
26 VDD48
25 GND
#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
XIN
XOUT
VTT_PWRGD
FS(0:4)
MODE &
SEL24_48# &
PD#*
PCI_STOP#*
CPU_STOP#*
SDATA*
SCLK*
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
VCOCLK
M/N/Ratio
ROM
Latch
&POR
Divider
Divider
Control
Logic
&Config
Register
I2C
Interface
48MHz
24_48MHz
3
REF 0:2
2 CPUCLKT0:1
CPUCLKC0:1
2
2
25MHz_0:1
3
AGP0:2
10 PCI_F0:2,PC
I_0:6
RESET#
Rref
-2-

6 Page









W83194BR-911 pdf, datenblatt
W83194BR-911, W83194BG-911
STEPLESS CLOCK FOR VIA PT/PM CHIPSET
Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh), continued
BIT PIN NO PWD
DESCRIPTION
3 21 1 PCI6 output control
2 20 1 PCI5 output control
1 17 1 PCI4 output control
0 16 1 PCI3 output control
7.4 Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)
BIT PIN NO PWD
DESCRIPTION
7 15 1 PCI2 output control
6 14 1 PCI1 output control
5 13 1 PCI0 output control
4 - 1 Don’t modify it
3 - 1 Don’t modify it
2 27 1 AGP_2 output control
1 30 1 AGP_1 output control
0 31 1 AGP_0 output control
7.5 Register 4: 24_48MHz, 48MHz, REF, 25MHz Control (1 = Enable, 0 = Stopped)
(Default: BFh)
BIT PIN NO PWD
DESCRIPTION
7 24 1 24_48MHz output control
6 - 0 Reserved
5 23 1 48MHz output control
4 3 1 REF2 output control
3 2 1 REF1 output control
2 1 1 REF0 output control
1 36 1 25MHz_1 output control
0 37 1 25MHz_0 output control
-8-

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