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PDF GS1574A Data sheet ( Hoja de datos )

Número de pieza GS1574A
Descripción HD-LINX-R II Adaptive Cable Equalizer
Fabricantes Gennum Corporation 
Logotipo Gennum Corporation Logotipo



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GS1574A HD-LINX® II
Adaptive Cable Equalizer
GS1574A Data Sheet
Features
• SMPTE 292M and SMPTE 259M compliant
• Automatic cable equalization
• Multi-standard operation from 143Mb/s to
1.485Gb/s
• Supports DVB-ASI at 270Mb/s
• Small footprint (4mm x 4mm)
• Pb-free and RoHS compliant
• Manual bypass (useful for low data rates with slow
rise/fall times)
• Performance optimized for 270Mb/s and 1.485Gb/s
• Typical maximum equalized length of Belden
1694A cable: 140m at 1.485Gb/s, 350m at 270Mb/s
• 50Ω differential output (with internal 50Ω pull-ups)
• Manual output mute or programmable mute based
on max cable length adjust
• Single 3.3V power supply operation
• Operating temperature range: 0°C to +70°C
Applications
• SMPTE 292M and SMPTE 259M Coaxial Cable
Serial Digital Interfaces.
Description
The GS1574A is a second-generation high-speed
BiCMOS integrated circuit designed to equalize and
restore signals received over 75Ω co-axial cable.
The GS1574A is designed to support SMPTE 292M and
SMPTE 259M, and is optimized for performance at
270Mb/s and 1.485Gb/s.
The GS1574A features DC restoration to compensate
for the DC content of SMPTE pathological test patterns.
A voltage programmable mute threshold (MCLADJ) is
included to allow muting of the GS1574A output when
an approximate selected cable length is reached for
SMPTE 259M signals. This feature allows the GS1574A
to distinguish between low amplitude SD-SDI signals
and noise at the input of the device. The serial digital
outputs of the GS1574A may be forced to a mute state
by applying a voltage to the MUTE pin.
Power consumption is typically 215mW using a 3.3V
power supply. The GS1574A is lead-free, and the
encapsulation compound does not contain halogenated
flame retardant.
This component and all homogeneous subcomponents
are RoHS compliant.
MCLADJ
SDI
SDI
CABLE LENGTH ADJUSTOR
CARRIER DETECT
MUTE
EQUALIZER
DC RESTORE
OUTPUT
AGC
GS1574A Functional Block Diagram
CD
MUTE
BYPASS
SDO
SDO
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GS1574A pdf
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
GS1574A Data Sheet
Parameter
Supply Voltage
Input ESD Voltage
Storage Temperature Range
Input Voltage Range (any input)
Operating Temperature Range
Solder Reflow Temperature
Value
-0.5V to +3.6 VDC
2kV
-50°C < Ts < 125°C
-0.3 to (VCC +0.3)V
0°C to 70°C
260°C
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown
Parameter
Supply Voltage
Power Consumption
Supply Current
Output Common Mode Voltage
Input Common Mode Voltage
MCLADJ DC Voltage (to mute
signal)
MCLADJ Range
CD Output Voltage
Symbol
VCC
PD
Is
VCMOUT
VCMIN
VCD(OH)
Mute Input Voltage Required to
Force Outputs to Mute
Mute Input Voltage Required to
Force Outputs Active
VCD(OL)
VMute
VMute
Conditions
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
0m, TA = 25°C
TA = 25°C
Carrier not
present
Carrier present
Min to Mute
Max to Activate
Min
3.135
2.4
2.0
Typ
3.3
215
65
VCC - ΔVSDO/2
1.75
1.3
0.5
Max
3.465
0.4
0.8
Units
V
mW
mA
V
V
V
Notes
±5%
V–
V–
V–
V–
V–
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GS1574A arduino
4. Detailed Description
GS1574A Data Sheet
The GS1574A is a high speed BiCMOS IC designed to equalize serial digital
signals.
The GS1574A can equalize both HD and SD serial digital signals, and will typically
equalize greater than 140m of Belden 1694A cable at 1.485Gb/s and 350m at
270Mb/s.
The GS1574A is powered from a single +3.3V power supply and consumes
approximately 215mW of power.
4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is
recommended, as the SDI and SDI inputs are internally biased at approximately
1.8V.
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic. In addition,
the variation of the frequency response with control voltage imitates the variation
of the inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an
internal and an external AGC filter capacitor providing a steady control voltage for
the gain stage. As the frequency response of the gain stage is automatically varied
by the application of negative feedback, the edge energy of the equalized signal is
kept at a constant level which is representative of the original edge energy at the
transmitter. The equalized signal is also DC restored, effectively restoring the logic
threshold of the equalized signal to its correct level independent of shifts due to AC
coupling. The digital output signals have a nominal voltage of 750mVpp differential,
or 375mVpp single ended when terminated with 50Ω as shown in Figure 4-1.
33416 - 5 March 2006
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