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PDF GS1531 Data sheet ( Hoja de datos )
| Número de pieza | GS1531 | |
| Descripción | HD-LINX-TM II Multi-Rate Serializer | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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Key Features
• SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ → NRZI encoding (with
bypass)
• DVB-ASI sync word insertion and 8b/10b encoding
• Superior rejection of jitter on input PCLK
• user selectable additional processing features
including:
• CRC, ANC data checksum, and line number
calculation and insertion
• TRS and EDH packet generation and insertion
• illegal code remapping
• internal flywheel for noise immune TRS generation
• 20-bit / 10-bit CMOS parallel input data bus
• 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital input
• automatic standards detection and indication
• 1.8V core power supply and 3.3V charge pump
power supply
• 3.3V digital I/O supply
• JTAG test interface
• Available in a Pb-free package
• small footprint (11mm x 11mm)
Applications
• SMPTE 292M Serial Digital Interfaces
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
GS1531 HD-LINX™ II
Multi-Rate Serializer
GS1531 Data Sheet
Description
The GS1531 is a multi-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1525 Voltage Controlled Oscillator, a transmit
solution can be realized for HD-SDI, SD-SDI and
DVB-ASI applications.
The device features an internal PLL, which can be
configured for loop bandwidth as narrow as 100kHz.
Thus the GS1531 can tolerate substantive jitter on the
input PCLK and still provide output jitter well within
SMPTE specification. Connect the output clocks from
Gennum’s GS4911 clock generator directly to the
GS1531’s PCLK input and configure the GS1531’s loop
bandwidth accordingly.
In addition to serializing the input, the GS1531 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats at both HD and SD
signal rates. An appropriate parallel clock input signal is
also required.
The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode, adjustable
signal swing, and automatic dual slew rate selection
depending on HD/SD operational requirements.
The GS1531 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
calculate and insert line numbers and CRC’s, re-map
illegal code words and insert SMPTE 352M payload
identifier packets. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.
30573 - 4 July 2005
1 of 49
www.gennum.com
1 page  
1. Pin Out
GS1531 Data Sheet
1.1 Pin Assignment
1 2 34 5
A LF
VCO_
VCC
VCO_
GND
VCO
VCO
B LB_
CP_CAP CP_VDD CP_GND CONT
NC
6 7 8 9 10
NC PCLK IO_VDD DIN18 DIN19
NC DETECT IO_GND DIN16 DIN17
_TRS
C NC PD_VDD PD_GND NC
NC NC
NC NC DIN14 DIN15
D NC
NC NC
NC DVB_ASI LOCKED NC
NC DIN12 DIN13
E NC
NC
NC
SD/HD
CORE
_GND
CORE
_VDD
NC IO_VDD DIN10 DIN11
F RSV NC
NC 20bit/ CORE CORE NC IO_GND DIN8 DIN9
10bit _GND _VDD
G NC
NC
NC IOPROC SMPTE_ RESET
_EN/DIS BYPASS _TRST
NC
BLANK DIN6 DIN7
H NC
NC NC
CS_
TMS
SCLK
_TCK
SDOUT
_TDO
NC
H DIN4 DIN5
J NC NC NC NC SDO_EN SDIN V IO_GND DIN2 DIN3
/DIS _TDI
K RSET CD_VDD SDO
SD0
CD_GND
JTAG/
HOST
F IO_VDD DIN0 DIN1
30573 - 4 July 2005
5 of 49
5 Page 
GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
H6
SDOUT_TDO
Synchronous
with
SCLK_TCK
H8 H Synchronous
with PCLK
J5 SDO_EN/DIS
Non
Synchronous
J6
SDIN_TDI
Synchronous
with
SCLK_TCK
Type Description
Output
Input
Input
Input
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data
when DETECT_TRS is set LOW. The device will set the H bit in all
outgoing TRS signals for the entire period that the H input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal should be set HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking period
as indicated by the H bit in the received TRS ID words, and LOW
otherwise.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
30573 - 4 July 2005
11 of 49
11 Page | ||
| Páginas | Total 49 Páginas | |
| PDF Descargar | [ Datasheet GS1531.PDF ] | |
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