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PDF ADS7863 Data sheet ( Hoja de datos )
| Número de pieza | ADS7863 | |
| Descripción | Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown | |
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BurrĆBrown Products
from Texas Instruments
ADS7863
ADS7863
ADS7863
SBAS383 – JUNE 2007
Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
• Four Fully- or Six Pseudo-Differential Inputs
• SINAD: 70dB (min), THD: –75dB (max)
• Programmable and Buffered Internal 2.5V
Reference
• Flexible Power-Down Features
• Variable Power Supply Ranges
• Low Power Operation: 40mW at 5V
• Operating Temperature Range: –40°C to
+125°C
• Pin-Compatible with ADS7861 and ADS8361
(SSOP package)
APPLICATIONS
• Motor Control
• Multi-Axis Positioning Systems
• Three-Phase Power Control
DESCRIPTION
The ADS7863 is a dual, 12-bit, 1.5MSPS,
analog-to-digital converter (ADC) with four fully
differential input channels grouped into two pairs for
high-speed, simultaneous signal acquisition. Inputs
to the sample-and-hold (S/H) amplifiers are fully
differential and are maintained differential to the input
of the ADC. This architecture provides excellent
common-mode rejection of 80dB at 50kHz, which is
a critical performance characteristic in noisy
environments.
The ADS7863 is pin-compatible with the ADS8361,
but offers additional features such as a
programmable reference output, flexible supply
voltage (2.7V to 5.5V for AVDD and 1.65V to 5.5V for
BVDD), a pseudo-differential input multiplexer with
three channels per ADC, and several power-down
features.
The high-speed, dual serial interface is also
pin-compatible with the ADS7861 while offering
additional flexibility. The ADS7863 is offered in an
SSOP-24 and a 4x4mm QFN-24 package. It is
specified over the extended operating temperature
range of –40°C to +125°C.
AVDD
CHA0+
CHA0-
CHA1+
CHA1-
CHB0+
CHB0-
CHB1+
CHB1-
REFIN
Input
MUX
Input
MUX
SAR
S/H CDAC
Comparator
S/H CDAC
Comparator
SAR
BVDD
SDOA
SDOB
M0
M1
SDI
CLOCK
CS
RD
BUSY
CONVST
BGND
REFOUT
AGND
10-Bit DAC
2.5V Reference
Functional Block Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
1 page  
ADS7863
www.ti.com
SBAS383 – JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +125°C, and AVDD = 5V, BVDD = 3.3V, VREF = 2.5V (internal), fCLK = 24MHz, and fSAMPLE = 1.5MSPS, unless
otherwise noted.
PARAMETER
INTERNAL VOLTAGE REFERENCE, continued
PSRR
Power-supply rejection ratio
IREFOUT
Reference output dc current
IREFSC
Reference output short-circuit current
tREFON
Reference output settling time
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage range
IREF Reference input current
CREF
Reference input capacitance
DIGITAL INPUTS
Logic family
VIH High-level input voltage
VIL Low-level input voltage
IIN Input current
CIN Input capacitance
DIGITAL OUTPUTS
Logic family
VOH High-level output voltage
VOL Low-level output voltage
IOZ High-impedance-state output current
COUT
Output capacitance
CLOAD
Load capacitance
POWER SUPPLY
AVDD
BVDD
Analog supply voltage
Buffer I/O supply voltage
AIDD
Analog supply current
BIDD
PDISS
Buffer I/O supply current
Power dissipation
TEST CONDITIONS
VIN = BVDD to BGND
IOH = –100μA
IOH = 100μA
VIN = BVDD to BGND
AVDD to AGND
BVDD to BGND
AVDD = 3V
AVDD = 5.5V
AVDD = 3V, NAP power-down
AVDD = 5.5V, NAP power-down
AVDD = 3V, deep power-down
AVDD = 5.5V, deep power-down
AVDD = 3V
AVDD = 5.5V
ADS7863
MIN
TYP (1)
MAX UNIT
dB
1 mA
mA
100 μs
0.5
2.5
2.525
V
50 μA
10 pF
0.7 × BVDD
–0.3
–50
CMOS
5
BVDD + 0.3
0.3 × BVDD
+50
V
V
nA
pF
BVDD – 0.2
–50
CMOS
5
V
0.2 V
+50 nA
pF
30 pF
2.7 5.0 5.5 V
1.65 3.3 5.5 V
67
78
μA
18.9
40
μA
μW
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5
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ADS7863
www.ti.com
APPLICATIONS INFORMATION
SBAS383 – JUNE 2007
GENERAL DESCRIPTION
The ADS7863 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 541.67ns. Adding
the acquisition time of 125ns results in a maximum
conversion rate of 1.5MSPS.
Each ADC has a fully differential, 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage
(for example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common pin and
the remaining three inputs (CHx0+, CHx1–, and
CHx1+) operate as separate inputs referred to the
common pin.
The ADS7863 also includes a 2.5V internal
reference. The reference drives a 10-bit
digital-to-analog converter (DAC), allowing the
voltage at the REFOUT pin to be adjusted via the
serial interface in 2.44mV steps. A low-noise
operational amplifier with unity gain buffers the DAC
output voltage and drives the REFOUT pin.
The ADS7863 offers a serial interface that is
compatible with the ADS7861. However, instead of
the A0 pin of the ADS7861 that controls the channel
selection, the ADS7863 offers a serial data input
(SDI) pin that supports additional functions described
in the Digital section of this data sheet.
ANALOG
This section addresses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer; see
Figure 15. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
shown in Table 2). The channel selection is
performed using bits C1 and C0 in the SDI Register
(see also the Serial Data Input section).
The input path for the converter is fully differential
and provides a common-mode rejection of 80dB at
50kHz. The high CMRR also helps suppress noise in
harsh industrial environments.
CHx1+
CHx1-
CHx0+
CHx0-
Input
MUX
ADC+
ADC-
Figure 15. Input Multiplexer Configuration
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
1
1
CHx1+
CHx1–
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
0
1
CHx1–
CHx0–
1
1
CHx1+
CHx0–
Each of the of 2pF sample-and-hold capacitors
(shown as CS in the Equivalent Input Circuit) is
connected via switches to the multiplexer output.
Opening the switches holds the sampled data during
the conversion process. After finishing the
conversion, both capacitors are pre-charged for the
duration of one clock cycle to the voltage present at
the REFIN pin. After the pre-charging, the multiplexer
outputs are connected to the sampling capacitors
again. The voltage at the analog input pin is usually
different from the reference voltage; therefore, the
sample capacitors must be charged to within
one-half LSB for 12-bit accuracy during the
acquisition time tACQ (see the Timing
Characteristics).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after finishing the previous conversion and
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 125ns.
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 12 being the resolution of the
ADS7863:
f-3dB =
ln(2) ´ (n + 1)
2p ´ tACQ
(1)
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11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADS7863.PDF ] | |
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