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AD9920A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9920A
Beschreibung 12-Bit CCD Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9920A Datasheet, Funktion
12-Bit CCD Signal Processor with V-Driver
and Precision Timing Generator
AD9920A
FEATURES
Integrated 19-channel V-driver
1.8 V AFETG core
24 programmable vertical clock signals
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
12-bit, 40.5 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip sync generator with external sync input
On-chip 1.8 V low dropout (LDO) regulator
105-ball, 8 mm × 8 mm CSP_BGA package
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9920A is a highly integrated charge-coupled device (CCD)
signal processor for digital still camera applications. It includes a
complete analog front end (AFE) with analog-to-digital conversion,
combined with a full-function programmable timing generator
and 19-channel vertical driver (V-driver). The timing generator
is capable of supporting up to 24 vertical clock signals to control
advanced CCDs. The on-chip V-driver supports up to 19 channels
for use with six-field CCDs. A Precision Timing® core allows adjust-
ment of high speed clocks with approximately 400 ps resolution
at 40.5 MHz operation. The AD9920A also contains six GPOs
that can be used for shutter and system functions.
The analog front end includes black level clamping, variable
gain CDS, and a 12-bit ADC. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
The AD9920A is specified over an operating temperature range
of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
–3dB, 0dB, +3dB, +6dB
CCDIN
CDS
VGA
LDOIN
LDOOUT
LDO
REG
6dB TO 42dB
VREF
12-BIT
ADC
CLAMP
12
AD9920A
D0 TO D11
DCLK
RG
HL
H1 TO H8
V1A TO V6 (3-LEVEL)
V7 TO V16 (2-LEVEL)
SUBCK
HORIZONTAL
8 DRIVERS
XV1 TO XV24
19
VERTICAL
DRIVER
24
GPO5
GPO6
VERTICAL
TIMING
CONTROL
XSUBCK 6
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SL
SCK
SDATA
XSUBCNT
GPO1 TO GPO4,
GPO7, GPO8
Figure 1.
HD VD
CLI CLO SYNC/RST
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.






AD9920A Datasheet, Funktion
AD9920A
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD1 and HVDD2 = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS (IOVDD)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (IOVDD, DRVDD)
High Level Output Voltage
Low Level Output Voltage
RG and H-DRIVER OUTPUTS (HVDD1,
HVDD2, and RGVDD)
High Level Output Voltage
Low Level Output Voltage
Maximum H1 to H8 Output Current
Maximum HL and RG Output Current
Maximum Load Capacitance
CLI INPUT
High Level Input Voltage
Low Level Input Voltage
Symbol
VIH
VIL
IIH
IIL
CIN
VOH
VOL
VOH
VOL
VIHCLI
VILCLI
Test Conditions/Comments Min
VDD − 0.6
IOH = 2 mA
IOL = 2 mA
VDD − 0.5
Typ
10
10
10
Maximum current
Maximum current
Programmable
Programmable
Each output
With CLO oscillator disabled
VDD − 0.5
30
17
60
CLIVDD/2 + 0.5
Max Unit
V
0.6 V
μA
μA
pF
V
0.5 V
V
0.5 V
mA
mA
pF
V
CLIVDD/2 − 0.5 V
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 40.5 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CDS1
DC Restore
Allowable CCD Reset Transient
CDS Gain Accuracy
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Maximum Input Range Before
Saturation
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Allowable OB Pixel Amplitude1
0 dB CDS Gain (Default)
+6 dB CDS Gain
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain
Maximum Gain
Test Conditions/Comments
Min
AVDD − 0.5 V
Limit is the lower of AVDD + 0.3 V or 2.2 V
VGA gain = 6.3 dB (Code 15, default value)
1.21
−3.1
−0.6
2.7
5.2
VGA Code 15, default
VGA Code 1023
−100
−50
Typ Max
1.3 1.44
0.5 0.8
−2.6 −2.1
−0.1 +0.4
3.2 3.7
5.7 6.2
1.4
1.0
0.7
0.5
+200
+100
1024
Guaranteed
6.3
42.4
Rev. B | Page 5 of 112
Unit
V
V
dB
dB
dB
dB
V p-p
V p-p
V p-p
V p-p
mV
mV
Steps
dB
dB

6 Page









AD9920A pdf, datenblatt
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER
INDEX AREA
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
BOTTOM VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type 1
L6
AVDD
P
J7, K8
AVSS
P
A10
DVDD
P
A9
DVSS
P
L5
CLIVDD
P
K6
TCVDD
P
K4
TCVSS
P
A2
DRVDD
P
B2 DRVSS/LDOVSS P
E1
HVDD1
P
E2
HVSS1
P
G1
HVDD2
P
G2
HVSS2
P
J1
HVDD2
P
J2
HVSS2
P
L3
RGVDD
P
K3
RGVSS
P
B1
LDOIN
P
C1
LDOOUT
P
H11
IOVDD
P
G11
IOVSS
P
C11
VDVDD
P
C10
VDVSS
P
E3 VM1 P
D3 VL1 P
C3 VH1 P
J3 VH2 P
H3 VL2 P
F3 VM2 P
G3
VMM
P
J4 VLL P
L7
CCDIN
AI
K7
CCDGND
AI
C2
SRCTL
AI
L8
REFT
AO
L9
REFB
AO
D11 VD
DIO
E10 HD
DIO
Description
Analog Supply.
Analog Supply Ground.
Digital Logic Supply.
Digital Logic Ground.
CLI Input Supply.
Analog Timing Core Supply.
Analog Timing Core Ground.
Data Driver Supply.
Data Driver and LDO Ground.
H-Driver Supply.
H-Driver Ground.
H-Driver Supply.
H-Driver Ground.
H-Driver Supply.
H-Driver Ground.
RG, HL Driver Supply.
RG, HL Driver Ground.
LDO 3.3 V Input.
LDO Output Voltage.
Digital I/O Supply.
Digital I/O Ground.
V-Driver Logic Supply (3 V).
V-Driver Ground.
V-Driver Midsupply.
V-Driver Low Supply.
V-Driver High Supply.
V-Driver High Supply.
V-Driver Low Supply.
V-Driver Midsupply.
V-Driver Midsupply for SUBCK Output.
V-Driver Low Supply for SUBCK Output.
CCD Signal Input.
CCD Ground.
Slew Rate Control Pin. Tie to VDVSS if not used.
Voltage Reference Top Bypass.
Voltage Reference Bottom Bypass.
Vertical Sync Pulse.
Horizontal Sync Pulse.
Rev. B | Page 11 of 112
AD9920A

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