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PDF DS34T102 Data sheet ( Hoja de datos )
| Número de pieza | DS34T102 | |
| Descripción | (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev: 072707
DS34T101/DS34T102/DS34T104/DS34T108
Single/Dual/Quad/Octal TDM-Over-Packet Chip
General Description
The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
draft-compliant DS34T108 allows up to eight T1/E1
links or frame-based serial HDLC links to be
transported transparently through a switched IP or
MPLS packet network. Jitter and wander of
recovered clocks conform to G.823/G.824, G.8261,
and TDM specifications. This eliminates the need for
remote timing sources in cabinets and pedestals.
The Ethernet side of the DS34T108 provides high
QoS capabilities to its MII/RMII/SSMII port, while the
WAN side supports full-featured T1/E1 framers and
LIUs. This takes the solution all the way through
analog, while preserving options to make use of TDM
streams at key intermediate points. The high level of
integration that the DS34T108 brings minimizes cost,
board space, and time to market.
Applications
TDM Circuit Extension Over PSN
o Leased—Line Services Over PSN
o TDM Over G/E—PON
o TDM Over Cable
o TDM Over WiMAX
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC—Based Traffic Transport Over PSN
Functional Diagram
CPU
Bus
DS34T108
Octal
T1/E1/J1
Transceiver
Framers
BERT
& CAS
LIUs
Circuit
Emulation
Engine
10/100
Ethernet
MAC
xMII
CLAD
Buffer
Manager
TDM
Access
Clock Inputs
SDRAM
Interface
Features
♦ Full-Featured T1/E1/J1 LIU/Framer/TDM-Over-
Packet
♦ Supports Adaptive Clock Recovery, Common
Clock (Using RTP), External Clock, and
Loopback Timing Modes
♦ Selectable 32-Bit or 16-Bit Processor Bus
♦ Clock Rate Adapter for T1/E1 Master Clock
♦ 10/100 Ethernet MAC That Supports
MII/RMII/SSMII
♦ Fully Compatible with IEEE 802.3 Standard
♦ VLAN Support According to 802.1 p&Q
♦ Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, and Metro
Ethernet
♦ End-to-End TDM Synchronization Through
the IP/MPLS Domain by Eight Independent
On-Chip TDM Clock Recovery Mechanisms
♦ Single Serial Support for RS-530 and V.35
♦ Single DS3/E3/STS-1 to Ethernet
♦ Packet Loss Compensation and Handling of
Misordered Packets
♦ 64 Independent Bundle/Connections
♦ Glueless SDRAM Buffer Management
♦ 1.8V Core, 3.3V I/O
♦ Complies with IETF PWE3 RFCs and Drafts
for CESoPSN, SAToP, TDMoIP, and HDLC
Features continued in Section 7.
Ordering Information
PART
PORTS TEMP RANGE
DS34T108GN
8 -40°C to +85°C
DS34T108GN+
8 -40°C to +85°C
DS34T104GN*
4 -40°C to +85°C
DS34T104GN+* 4 -40°C to +85°C
DS34T102GN*
2 -40°C to +85°C
DS34T102GN+* 2 -40°C to +85°C
DS34T101GN*
1 -40°C to +85°C
DS34T101GN+* 1 -40°C to +85°C
+Denotes a lead-free package.
*Future product—Contact factory for availability.
PIN-
PACKAGE
484 HSBGA
484 HSBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about
device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim
Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
List of Tables
Table 3-1. T1-Related Telecommunications Specifications ........................................................................................ 9
Table 3-2. E1-Related Telecommunications Specifications ...................................................................................... 10
Table 3-3. TDM-over-Packet Related Specifications................................................................................................. 11
Table 10-1. DS34T108 Short Pin Descriptions.......................................................................................................... 28
Table 10-2. Detailed Pin Descriptions ....................................................................................................................... 35
Table 11-1. JTAG Instruction Codes ......................................................................................................................... 52
Table 11-2. JTAG ID Code ........................................................................................................................................ 52
Table 12-1. Recommended DC Operating Conditions .............................................................................................. 54
Table 12-2. DC Electrical Characteristics.................................................................................................................. 54
Table 14-1. Common Board Design Connections ..................................................................................................... 56
5 of 74
5 Page 
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
Table 3-3. TDM-over-Packet Related Specifications
Y.1413 TDM-MPLS network interworking – User plane interworking
TDMoMPLS will meet standards for network interworking that covers the Transport label, Interworking label, Common
interworking indicators, and Optional timing information. The Common interworking indicators include a Control Field, a
Fragmentation Field, Length Indicator and the Sequence number.
TDMoMPLS shall meet standards for Structure Agnostic transport.
TDMoMPLS shall meet standards for Structure Aware transport that contains Structure-locked encapsulation and Structure-
indicated encapsulation.
Y.1414 Voice Service – MPLS network interworking
The recommendation focuses on the required functions and procedures necessary for support of narrow-band voice services
by MPLS networks. Details of the encapsulation of encoded audio streams in MPLS packets are specified. Clause 10 draft
recommendation shall be met.
Y.1452 (Y.VTOIP) Voice trunking over IP
This recommendation specifies a method for transporting multiplexed voice services over UDP/IP.
Y.1453 (Y.TDMIP) TDM-IP interworking – User plane interworking
This recommendation specifies methods for transporting low-rate TDM (T1, E1, T3, E3) over UDP/IP. Y.1453 is a direct
extension of Y.1413.
PWE3-CESoPSN Structure-aware TDM Circuit Emulation Service over Packet Switched Network
May 2006 ‘draft-ietf-pwe3-cesopsn-07.txt’ revision shall be supported.
The TDM-over-Packet shall meet Basic NxDS0 service, and "Trunk-specific" NxDS0 service with CAS.
The TDM-over-Packet shall meet CESoPSN packet format for an IPv4/IPv6 PSN, CESoPSN Packet Format for an MPLS PSN.
Shall also meet CESoPSN Payload Layer.
PWE3-SAToP Structure-Agnostic TDM over Packet
June 2006 ‘rfc4553.txt’ revision shall be supported.
The TDM-over-Packet shall meet Basic SAToP Packet format, SAToP Packet format for an IPv4/IPv6, SAToP Packet format
for a MPLS PSN, and SAToP Payload Layer. SATop Control Word.
PWE3-TDMoIP
December 2006 ‘draft-ietf-pwe3-tdmoip-06.txt’ revision shall be supported.
PWE3-HDLC
September 2006 ‘rfc4618.txt’ revision shall be supported. (excluding clause 4.3 – PPP)
IEEE 802.3
This standard covers the MAC interface to a PHY for MII.
MPLS-Frame Relay Alliance Implementation Agreements 4.1
The purpose of this Implementation Agreement (IA) is to define network interworking between TDM circuits (n x 64 kbps,
E1/T1/E3/T3) over MPLS Label Switched Paths (LSPs) by using AAL1 encapsulation.
MPLS-Frame Relay Alliance Implementation Agreements 5.1
This specification defines MPLS support for the transport of AAL type 2 CPS-Packets. Frame formats and
procedures required for this transport are described in this Implementation Agreement. This specification addresses the
transport of any AAL type 2 CPS-Packets regardless of the application data that is transported.
MPLS-Frame Relay Alliance Implementation Agreements 8.0.0
This document describes a method for encapsulating TDM signals belonging to the PDH hierarchy (T1, E1, T3, E3, Nx64kbps)
as pseudo-wires over a MPLS network.
MEF 8 – Metro Ethernet Forum 8 - Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet
Networks
This document provides an implementation agreement for the emulation of PDH services across a Metro Ethernet Network.
Specifically it covers emulation of Nx64kbps, DS1, E1, DS3 and E3 circuits. Generically this is referred to as Circuit Emulation
Services over Ethernet (CESoETH).
G.823/G.824 Jitter & Wander Requirements
G.8261/Y.1361 (G.pactiming) Timing and Synchronization Aspects in Packet Networks
This recommendation defines synchronization aspects in packet networks and specifies the maximum network limits of jitter
and wander that shall not be exceeded and the minimum equipment tolerance to jitter and wander than shall be provided at the
boundary of these packet networks at TDM interfaces. It also outlines the minimum requirements for the synchronization
function of network elements.
11 of 74
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DS34T102.PDF ] | |
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