PDF DS3105 Data sheet ( Hoja de datos )

Número de pieza	DS3105
Descripción	Line Card Timing IC
Fabricantes	Maxim Integrated Products
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No Preview Available ! www.DataSheet4U.com Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs and performs automatic hitless reference switching if the primary reference fails. The highly programmable DS3105 supports numerous input and output frequencies including frequencies required for SONET/SDH, Synchronous Ethernet (1G, 10G and 100Mb/s), wireless basestations and CMTS systems. PLL bandwidths from 18 Hz to 400 Hz are supported, and a wide variety of PLL characteristics and device features can be configured to meet the needs of many different applications. The DS3105 register set is backward compatible with Semtech’s ACS8525 line card timing IC. The DS3105 pinout is similar but not identical to the ACS8525. APPLICATIONS SONET/SDH, Synchronous Ethernet, PDH and Other Line Cards in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations. FUNCTIONAL DIAGRAM LVDS/LVPECL or CMOS/TTL IC3 IC4 IC5 IC6 IC9 SYNC1 SYNC2 SYNC3 local oscillator DS3105 control status OC3 OC6 LVDS/LVPECL FSYNC MFSYNC FEATURES Advanced DPLL Technology Programmable PLL bandwidth: 18 Hz to 400 Hz Hitless Reference Switching, Automatic or Manual Holdover on Loss of All Input References Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless and CMTS Rates 5 Input Clocks Two CMOS/TTL (≤125 MHz) Two LVDS/LVPECL/CMOS/TTL (≤156.25 MHz) Backup Input (CMOS/TLL) in Case of Complete Loss of System Timing References Three Optional Frame Sync Inputs (CMOS/TTL) Continuous Input Clock Quality Monitoring Numerous Input Clock Frequencies Supported - SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz - Ethernet xMII: 2.5, 25, 125, 156.25 MHz - PDH: N x DS1, N x E1, N x DS2, DS3, E3 - Frame Sync: 2 kHz, 4 kHz, 8 kHz - Custom: Any Multiple of 2 kHz up to 131.072 MHz, Any Multiple of 8 kHz up to 155.52 MHz 2 Output Clocks One CMOS/TTL Output (≤125 MHz) One LVDS/LVPECL Output (≤312.50 MHz) Two Optional Frame Sync Outputs: 2 kHz, 8 kHz Numerous Output Clock Frequencies Supported - SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz - Ethernet xMII: 2.5, 25, 125, 156.25, 312.5 MHz - PDH: N x DS1, N x E1, N x DS2, DS3, E3 - Other: 10, 10.24, 13, 30.72 MHz, plus other frequencies available upon request - Frame Sync: 2 kHz, 8 kHz - Custom Clock Rates: Any Multiple of 2 kHz up to 77.76 MHz, Any Multiple of 8 kHz up to 311.04 MHz General Suitable line card IC for stratum 3E/3/4, SMC, SEC Internal Compensation for Master Clock Oscillator SPI Processor Interface 1.8V Operation with 3.3V I/O (5V tolerant) Industrial Operating Temperature Range ORDERING INFORMATION PART DS3105LN DS3105LN+ TEMP RANGE -40 to 85°C -40 to 85°C PACKAGE LQFP64 LQFP64, RoHS compliant Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. 1 of 110 REV: 061507 1 page Preliminary. Subject to Change Without Notice. DS3105 LIST OF TABLES Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 11 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 11 Table 6-3. Global Pin Descriptions ............................................................................................................................ 12 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 13 Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 13 Table 6-6. Power Supply Pin Descriptions ................................................................................................................ 13 Table 7-1. Input Clock Capabilities ............................................................................................................................ 17 Table 7-2. Locking Frequency Modes ....................................................................................................................... 17 Table 7-3. Default Input Clock Priorities .................................................................................................................... 20 Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 26 Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 30 Table 7-6. Output Clock Capabilities ......................................................................................................................... 31 Table 7-7. Digital1 Frequencies................................................................................................................................. 32 Table 7-8. Digital2 Frequencies................................................................................................................................. 33 Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 33 Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 33 Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 33 Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 34 Table 7-13. OC3 and OC6 Output Frequency Selection ........................................................................................... 34 Table 7-14. Possible Frequencies for Programmable Outputs ................................................................................. 35 Table 7-15 T0CR1.T0FREQ Default Settings ........................................................................................................... 37 Table 7-16 T4CR1.T4FREQ Default Settings ........................................................................................................... 37 Table 7-17 OC6 Default Frequency Configuration .................................................................................................... 37 Table 7-18 OC3 Default Frequency Configuration .................................................................................................... 37 Table 7-19. External Frame Sync Source ................................................................................................................. 40 Table 8-1. Register Map ............................................................................................................................................ 45 Table 9-1. JTAG Instruction Codes ........................................................................................................................... 95 Table 9-2. JTAG ID Code .......................................................................................................................................... 96 Table 10-1. Recommended DC Operating Conditions .............................................................................................. 97 Table 10-2. DC Characteristics.................................................................................................................................. 97 Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 98 Table 10-4. LVDS/LVPECL Input Pins ...................................................................................................................... 98 Table 10-5. LVDS Output Pins .................................................................................................................................. 98 Table 10-6. LVPECL Level-Compatible Output Pins................................................................................................. 98 Table 10-7. Input Clock Timing................................................................................................................................ 100 Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 100 Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode............................................................ 100 Table 10-10. SPI Interface Timing ........................................................................................................................... 101 Table 10-11. JTAG Interface Timing........................................................................................................................ 102 Table 10-12. Reset Pin Timing ................................................................................................................................ 103 Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 104 Table 12-1. LQFP Thermal Properties, Natural Convection.................................................................................... 107 Table 12-2. LQFP Theta-JA (θJA) vs. Airflow ........................................................................................................... 107 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. 5 of 110 5 Page Preliminary. Subject to Change Without Notice. DS3105 6 PIN DESCRIPTIONS Table 6-1. Input Clock Pin Descriptions Pin Name(1) REFCLK IC3 IC4 IC5POS, IC5NEG IC6POS, IC6NEG IC9 SYNC1 SYNC2 SYNC3 / O3F0 Type(2) I IPD IPD IDIFF IDIFF IPD IPD IPD IPU Pin Description Reference Clock. Connect to a 12.800 MHz, high-accuracy, high-stability, low-noise local oscillator (XO or TCXO). See section 7.3. Input Clock 3. CMOS/TTL. Programmable frequency (default 8 kHz). This input can be associated with the SYNC1 pin. Input Clock 4. CMOS/TTL. Programmable frequency (default 8 kHz). This input can be associated with the SYNC2 pin. Input Clock 5. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz). LVDS/LVPECL: see Table 10-4, Figure 10-1 and Figure 10-2. CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS. This input can be associated with the SYNC1 pin. Input Clock 6. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz). LVDS/LVPECL: see Table 10-4, Figure 10-1 and Figure 10-2. CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS. This input can be associated with the SYNC2 pin. Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44 MHz). This input can be associated with the SYNC3 pin. Frame Sync1 Input. 2 kHz, 4 kHz or 8 kHz. FSCR3:SOURCE != 11XX This pin is the external frame sync input associated with any input pin using the FSCR3:SOURCE field. FSCR3:SOURCE = 11XX This pin is the external frame sync signal associated with IC3 or IC5 depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Frame Sync2 Input. 2 kHz, 4 kHz or 8 kHz. FSCR3:SOURCE != 11XX This pin is not used for the external frame sync signal. FSCR3:SOURCE = 11XX This pin is the external frame sync signal associated with IC4 or IC6 depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Frame Sync3 Input. 2 kHz, 4 kHz or 8 kHz. / OC3 Frequency Select 0. This pin is sampled when the RST pin goes high and the value is used as O3F0 which together with O3F2 and O3F1 sets the default frequency of the OC3 output clock pin. See Table 7-18. After RST goes high this pin becomes the SYNC3 input pin (2, 4 or 8 kHz) associated with IC9. It is only used as SYNC3 when FSCR2.SOURCE = 11XX. Table 6-2. Output Clock Pin Descriptions Pin Name(1) OC3 OC6POS, OC6NEG FSYNC MFSYNC Type(2) O ODIFF O3 O3 Pin Description Output Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by O3F[2:0] pins when the RST pin goes high, 19.44 MHz if O3F[2:0] pins left open). See Table 7-18. Output Clock 6. LVDS/LVPECL. Programmable frequency. Default frequency selected by O6F[2:0] pins when the RST pin goes high, 38.88 MHz if O6F[2:0] pins left open). The output mode is selected by MCR8.OC6SF[1:0]. See Table 10-5, Table 10-6 , Figure 10-1 and Figure 10-3. 8 kHz FSYNC. CMOS/TTL. 8 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse polarity and width are selectable using FSCR1.8KINV and FSCR1.8KPUL. 2 kHz MFSYNC. CMOS/TTL. 2 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse polarity and width are selectable using FSCR1.2KINV and FSCR1.2KPUL. Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. 11 of 110 11 Page

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