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DS3101 Schematic ( PDF Datasheet ) - Dallas Semiconductor

Teilenummer DS3101
Beschreibung Stratum 3/3E Timing Card IC
Hersteller Dallas Semiconductor
Logo Dallas Semiconductor Logo 




Gesamt 30 Seiten
DS3101 Datasheet, Funktion
www.DataSheet4U.com
www.maxim-ic.com
GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3101 is a highly integrated central timing and
synchronization solution for SONET/SDH network
elements. With 14 input clocks, the device directly
accepts both line timing from a large number of line
cards and external timing from external DS1/E1 BITS
transceivers. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 3
and 3E requirements of GR-1244, GR-253, and the
requirements of G.812 Type III and G.813. From the
output of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3101 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3101 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs. The DS3101 is functionally equivalent
to a DS3100 without integrated BITS transceivers.
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM
LINE CARDS AND
BITS/SSU RECEIVERS 14
(VARIOUS RATES)
DS3101
SONET/SDH
SYNCHRONIZATION
IC
11
TIMING TO
LINE CARDS AND
BITS/SSU TRANSMITTERS
(VARIOUS RATES)
LOCAL TCXO
OR OCXO
CONTROL STATUS
DS3101
Stratum 3/3E Timing Card IC
FEATURES
Synchronization Subsystem for Stratum 3E, 3,
4E, and 4, SMC and SEC
- Meets Requirements of GR-1244 Stratum 3/3E,
GR-253, G.812 Types I, III, and IV, and G.813
- Stratum 3E Holdover Accuracy with Suitable
External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks To and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
ORDERING INFORMATION
PART
TEMP RANGE
DS3101GN -40°C to +85°C
DS3101GN+ -40°C to +85°C
+Denotes a lead-free package.
PIN-PACKAGE
256 CSBGA (17mm)2
256 CSBGA (17mm)2
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 061307






DS3101 Datasheet, Funktion
DS3101 Stratum 3/3E Timing Card IC
1. STANDARDS COMPLIANCE
Table 1-1. Applicable Telecom Standards
SPECIFICATION
ANSI
T1.101
T1.102
TIA/EIA-644-A
ETSI
EN 300 417-6-1
EN 300 462-3-1
EN 300 462-5-1
IEEE
IEEE 1149.1
ITU-T
G.781
G.783
G.812
G.813
G.823
G.824
G.825
TELCORDIA
GR-253-CORE
GR-378-CORE
GR-1244-CORE
SPECIFICATION TITLE
Synchronization Interface Standard, 1999
Digital Hierarchy—Electrical Interfaces, 1993
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001
Transmission and Multiplexing (TM); Generic Requirements of Transport Functionality of
Equipment; Part 6-1: Synchronization Layer Functions, v1.1.3 (1999-05)
Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks;
Part 3-1: The Control of Jitter and Wander within Synchronization Networks, v1.1.1 (1998-05)
Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks;
Part 5-1: Timing Characteristics of Slave Clocks Suitable for Operation in Synchronous Digital
Hierarchy (SDH) Equipment, v1.1.1 (1998-05)
Standard Test Access Port and Boundary-Scan Architecture, 1990
Synchronization Layer Functions (06/1999)
ITU G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional
Blocks (10/2000 plus Amendment 1 06/2002 and Corrigendum 2 03/2003)
Timing Requirements of Slave Clocks Suitable for Use as Node Clocks in Synchronization
Networks (06/1998)
Timing characteristics of SDH equipment slave clocks (SEC) (03/2003)
The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps
Hierarchy (03/2000)
The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps
Hierarchy (03/2000)
The Control of Jitter and Wander within Digital Networks which are Based on the
Synchronous Digital Hierarchy (SDH) (03/2000)
SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000
Generic Requirements for Timing Signal Generators, Issue 2, February 1999
Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000
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DS3101 pdf, datenblatt
DS3101 Stratum 3/3E Timing Card IC
6. PIN DESCRIPTIONS
Table 6-1. Input Clock Pin Descriptions
PIN
NAME(1)
TYPE(2)
FUNCTION
H1 REFCLK
P6 IC1A
A10 IC1
P7 IC2A
B10 IC2
I
Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise
local oscillator (TCXO or OCXO). See Section 7.3.
I
Input Clock 1 AMI. AMI 64kHz composite clock. Enabled when MCR5:IC1SF = 0.
See Section 7.10.1, Table 10-6, and Figure 10-3.
IPD
Input Clock 1. CMOS/TTL. Programmable frequency (default 8kHz). Enabled when
MCR5:IC1SF = 1. See Section 7.10.1.
I
Input Clock 2 AMI. AMI 64kHz composite clock. Enabled when MCR5:IC2SF = 0.
See Section 7.10.1, Table 10-6, and Figure 10-3.
IPD
Input Clock 2. CMOS/TTL. Programmable frequency (default 8kHz). Enabled when
MCR5:IC2SF = 1. See Section 7.10.1.
C10 IC3
IPD Input Clock 3. CMOS/TTL. Programmable frequency (default 8kHz).
A11 IC4
IPD Input Clock 4. CMOS/TTL. Programmable frequency (default 8kHz).
B5 IC5POS
Input Clock 5. LVDS/LVPECL. Programmable frequency (default 19.44MHz LVDS).
IA, IA LVDS: See Table 10-4 and Figure 10-1.
A5 IC5NEG
LVPECL: See Table 10-5 and Figure 10-2.
B4
IC6POS
IA, IA
Input Clock 6. LVDS/LVPECL. Programmable frequency (default 19.44MHz
LVPECL).
LVDS: See Table 10-4 and Figure 10-1.
A4 IC6NEG
LVPECL: See Table 10-5 and Figure 10-2.
B11 IC7
IPD Input Clock 7. CMOS/TTL. Programmable frequency (default 19.44MHz).
C11 IC8
IPD Input Clock 8. CMOS/TTL. Programmable frequency (default 19.44MHz).
A12 IC9
IPD Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44MHz).
B12 IC10
A13 IC11
C12 IC12
IPD Input Clock 10. CMOS/TTL. Programmable frequency (default 19.44MHz).
IPD
Input Clock 11. CMOS/TTL. Programmable frequency (default 19.44MHz in master
mode, 6.48MHz in slave mode).
IPD Input Clock 12. CMOS/TTL. Programmable frequency (default 1.544/2.048MHz).
B13 IC13
IPD Input Clock 13. CMOS/TTL. Programmable frequency (default 1.544/2.048MHz).
A14 IC14
IPD Input Clock 14. CMOS/TTL. Programmable frequency (default 1.544/2.048MHz).
B14 SYNC2K
IPD Frame Sync Input. 2kHz, 4kHz, or 8kHz.
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