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PDF DS28EC20 Data sheet ( Hoja de datos )
| Número de pieza | DS28EC20 | |
| Descripción | 20Kb 1-Wire EEPROM | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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GENERAL DESCRIPTION
The DS28EC20 is a 20480-bit, 1-Wire® EEPROM
organized as 80 memory pages of 256 bits each. An
additional page is set aside for control functions.
Data is written to a 32-byte scratchpad, verified, and
then copied to the EEPROM memory. As a special
feature, blocks of eight memory pages can be write
protected or put in EPROM-Emulation mode, where
bits can only be changed from a 1 to a 0 state. The
DS28EC20 communicates over the single-conductor
1-Wire bus. The communication follows the standard
1-Wire protocol. Each device has its own unalterable
and unique 64-bit ROM registration number that is
factory lasered into the chip. The registration number
is used to address the device in a multidrop 1-Wire
net environment.
APPLICATIONS
Device Authentication
IEEE 1451.4 Sensor TEDS
Ink/Toner Cartridges
Medical Sensors
PCB Identification
Wireless Base Stations
ORDERING INFORMATION
PART
TEMP RANGE
PIN-
PACKAGE
DS28EC20+ -40°C to +85°C 3 TO-92
DS28EC20+T -40°C to +85°C 3 TO-92, T&R
+ Denotes a lead-free package.
T = tape and reel
TYPICAL OPERATING CIRCUIT
VCC
RPUP (300Ω
to 2.2kΩ)
PX.Y
µC
I/O
DS28EC20
GND
DS28EC20
20Kb 1-Wire EEPROM
FEATURES
20480 Bits of Nonvolatile (NV) EEPROM
Partitioned into Eighty 256-Bit Pages
Individual 8-Page Groups of Memory Pages
(Blocks) can be Permanently Write Protected or
Put in OTP EPROM-Emulation Mode ("Write to
0")
Read and Write Access Highly Backward-
Compatible to Legacy Devices (e.g., DS2433)
256-Bit Scratchpad with Strict Read/Write
Protocols Ensures Integrity of Data Transfer
200k Write/Erase Cycle Endurance at +25°C
Unique Factory-Programmed 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Communicates to Host at 15.4kbps or 125kbps
Using 1-Wire Protocol
Low-Cost TO-92 Package
Operating Range: 5V ±5%, -40°C to +85°C
IEC 1000-4-2 Level 4 ESD Protection (8kV
Contact, 15kV Air, Typical) for I/O Pin
PIN CONFIGURATION
DALLAS
28EC20
PIN 1 ---------- GND
PIN 2 ---------- I/O
PIN 3 ---------- N.C.
123
FOR TAPE-AND-
REEL THE LEADS
ARE FORMED TO
100 MILS (2.54mm)
SPACING VERSUS
50 MILS (1.27mm)
FOR BULK.
123
BOTTOM VIEW
Commands, bytes, and modes are capitalized for
clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp., a
wholly owned subsidiary of Maxim Integrated products, Inc.
1 of 24
REV: 071007
1 page  
DS28EC20: 20Kb 1-Wire EEPROM
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28EC20. The DS28EC20 has four main data components: 1) 64-bit registration number, 2) 32-byte scratchpad,
3) eighty 32-byte pages of EEPROM, and 4) special function registers. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. The bus master must first provide one of the seven ROM (network) function
commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive Skip ROM, or
7) Overdrive Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the
device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol
required for these ROM function commands is described in Figure 9. After a ROM function command is
successfully executed, the memory functions become accessible and the master may provide any one of the five
memory function commands. The protocol for these commands is described in Figure 7. All data is read and written
least significant bit first.
Figure 2. Hierarchical Structure for 1-Wire Protocol
DS28EC20 Command Level:
1-Wire ROM Function
Commands (see Figure 9)
DS28EC20-Specific
Memory Function
Commands (see Figure 7)
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Data Field
Affected:
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
Extended Read Mem.
32-byte Scratchpad, Flags
32-byte Scratchpad
Data Memory, Register Page
Data Memory, Register Page
Data Memory, Register Page
64-BIT LASERED ROM
Each DS28EC20 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register
and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire
CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas
Semiconductor iButton® Products (www.maxim-ic.com/AN27).
The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the last
bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 3. 64-Bit Lasered ROM
MSB
8-Bit
CRC Code
MSB
LSB
MSB
48-Bit Serial Number
LSB
8-Bit Family
Code (43h)
LSB MSB
LSB
iButton is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated products, Inc.
5 of 24
5 Page 
Figure 7-2. Memory Function Flow Chart (continued)
DS28EC20: 20Kb 1-Wire EEPROM
From Figure 7,
1st Part
AAh
Read Scratch-
Pad ?
N
Y
Bus Master RX
TA1 (T[7:0]), TA2 (T[15:8])
and E/S Byte
DS28EC20 sets Scratch-
pad Offset = (T[4:0])
Bus Master RX Data Byte
from Scratchpad Offset
DS28EC20
Increments
Scratchpad
Offset
Master
TX Reset ?
Y
N
N
Scrpad. Offset
= 11111b ?
Y
Bus Master RX CRC16 of
Command, Address, E/S
Byte, Data Bytes as sent
by the DS28EC20
Bus Master N
Master
RX “1”s
TX Reset ?
Y
To Figure 7,
3rd Part
See note in Write
Scratchpad flow chart
for additional details.
To Figure 7,
1st Part
11 of 24
From Figure 7,
3rd Part
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet DS28EC20.PDF ] | |
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