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PDF DS2705 Data sheet ( Hoja de datos )
| Número de pieza | DS2705 | |
| Descripción | SHA-1 Authentication Master | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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GENERAL DESCRIPTION
The DS2705 provides the master side of a Secure
Hash Algorithm (SHA) based token authentication
scheme. Hardware-based SHA authentication allows
for security without the added cost and complexity of
a microprocessor-based system. Batteries and other
accessories are authenticated using a single contact
through the Dallas 1-WireÒ interface. Authentication
is performed on demand or automatically, with the
pass/fail status reported on open-drain output pins to
signal the charge system and/or drive LEDs. The
DS2705 stores a predetermined challenge-and-
response pair in nonvolatile (NV) EEPROM. The
DS2705 works in conjunction with Dallas Battery
Management SHA-1 token products, including the
DS2703 and DS2704.
APPLICATIONS
Digital Cameras
Portable DVD and Media Players
Cradle and Accessory Chargers
Cell Phones/Smartphones
APPLICATION EXAMPLE
DS2705
SHA-1 Authentication Master
PIN CONFIGURATION
CHAL
PASS
FAIL
VSS
18
27
36
45
mMAX
VDD
MDQ
SDQ
VPP
FEATURES
§ Initiates Challenge-and-Response
Authentication based on the SHA-1 Algorithm
§ Dallas 1-Wire Master/Slave Interface Operates
at Standard and Overdrive Speeds
§ Input and Output pins for Initiating Challenge
and Reporting Authentication Pass/Fail
§ Programmable Configuration
§ Operates from 2.5V to 5.5V Supply
§ Tiny mMAX Package (Pb-Free)
ORDERING INFORMATION
PART
TEMP RANGE
DS2705U+
-40°C to +85°C
DS2705U+/T&R -40°C to +85°C
MARKING
DS2705
DS2705
PIN-PACKAGE
mMAX
DS2705U+ in Tape-and-Reel
+ Denotes lead-free package.
1-Wire is a registered trademark of Dallas Semiconductor.
1 of 18
050506
1 page  
AC ELECTRICAL CHARACTERISTICS
(2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
Programming Pulse Width
tPPW
Programming Pulse Rise Time
tPPR (Note 8)
Programming Pulse Fall Time
tPPF (Note 8)
Strong Pullup Delay Time
tSPUD
Strong Pullup Period
tSPUP
Challenge Delay Time
tCHD
Authentication Attempt Time
FAIL Pin Pulse Frequency
tAAT (Note 9)
tFPF FOM = 1, 50% duty cycle
DS2705: SHA-1 Authentication Master
MIN TYP MAX UNITS
17 ms
0.5 5
0.5 5
2 10
ms
ms
ms
24 34 48
ms
45 65 85
ms
61 490 ms
1.5 2 2.5
Hz
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
All voltages are referenced to VSS.
IDD3 Sleep mode conditions:
CHAL pin inactive OR (CHAL active AND (PAA = 0 AND PPT = 00 AND FOM = 0 AND Initial Authentication sequence
complete))
[Above conditions disable the internal oscillator]
Programming temperature range is TA = 0°C to 50°C.
5 years data retention at 70°C
If CHAL pin left unconnected, CHP bit = 0 required for an authentication attempt to be initiated on power up. See Table 1.
Typical Communication mode MDQ pullup behavior equivalent to 3kW resistor.
Typical Computation mode MDQ pullup behavior approximates a 50W resistor.
Exceeding maximum rise and fall time specifications may affect device reliability.
tAAT = Retries per Attempt x (264bits x 90ms + 3 x (tMRSTL + tRSTH) + tSPUD) = [1 to 8] x (23.7ms + 3.54ms + 34ms)
MAX[7 retries]: 490ms, MIN[no retries]: 61ms with standard timings
1. 1-Wire Master timings based on ±25% clock tolerance from nominal.
2. tRPDT [defined in design documentation] = tMRSTL + tMRSTH
3. tMPDL-MAX = tMRSTH-MIN – tMPDH-MAX, represents the maximum presence pulse low time allowed from the slave.
4. Bus rise time of ~1ms required to settle to logic high by tMRDV after MDQ released at tMLOW1
PIN DESCRIPTION
PIN
mMAX
1
TDFN
1
22
33
44
55
SYMBOL
CHAL
PASS
FAIL
VSS
VPP
6 6 SDQ
7 7 MDQ
8 8 VDD
FUNCTION
Challenge Strobe Input Pin. Initiates authentication. Active level/edge set by CHP bit.
Authentication “PASS” Result Open-Drain Output Pin
Authentication “FAIL” Result Open-Drain Output Pin (Programmable As Low Or Pulse)
Supply Return Pin, GND Reference for Logic Signals
EEPROM Programming Voltage Input
Slave Serial interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps or
143kbps. Bus master must provide a weak pullup.
Master Serial interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps or
143kbps. Provides a weak pullup in communication mode and strong pullup in
computation mode.
Supply Input Pin. Bypass to VSS with 0.1mF capacitor.
5 of 18
5 Page 
MAC Comparison
DS2705: SHA-1 Authentication Master
After the SHA-1 computation is completed by the remote token, the DS2705 and remote SHA-1 token both contain
a MAC result based on the secret key. The results are compared by the DS2705 on a bit by bit basis as the MAC
data is read in from the remote token. Note that the secret is never transmitted on the bus and thus cannot be
captured by observing bus traffic.
Multiple Authentication Attempts
The DS2705 is configurable for multiple authentication attempts or re-tries to avoid reporting authentication failure
in the event of contact bounce or a noisy communication channel. When configured for more than one retry, the
status outputs are kept at the previous state until one attempt succeeds or all attempts fail. It is always
recommended to configure the DS2705 for at least one retry.
Signaling Authentication Results
Authentication results are signaled on the open drain PASS and FAIL output pins. During an authentication attempt,
both outputs remain at their previous state. After authentication is complete, the pass or fail status is reported until
the display is cleared by one of the following conditions:
§ CHAL pin returning to inactive logic level.
§ Battery token removal detected when no 1-Wire Presence Pulse is returned in response to a 1-Wire
Reset.
Table 4. PASS/FAIL Outputs
CONDITION
FOM BIT
Token Not Present
x
Authentication in
Progress
x
Complete: Pass
x
Complete: Fail
0
1
PASS OUTPUT
Hi-Z
No Change
LOW
Hi-Z
Hi-Z
FAIL OUTPUT
Hi-Z
No Change
Hi-Z
LOW
Pulse
PROGRAMMING AND CONFIGURING
The DS2705 requires a configuration step prior to deployment to program the 64-bit challenge, 160-bit response
and to set up desired configuration options. Configuration is performed in slave mode using the SDQ and VPP
pins. The Challenge-and-Response pair, and option data are programmed in on-chip EEPROM that requires an
externally supplied programming voltage. After programming and verifying the EEPROM data, setting of the Lock
bits is recommended to prevent future modification. SDQ and VPP have internal pull downs which prevent the pins
from floating during normal operation.
11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet DS2705.PDF ] | |
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