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DS2704 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS2704
Beschreibung 1280-Bit EEPROM
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 18 Seiten
DS2704 Datasheet, Funktion
www.DataSheet4U.com
DS2704
1280-Bit EEPROM with SHA-1 Authentication
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2704 provides 1280 bits of EEPROM data
storage and a Secure Hash Algorithm (SHA) engine.
The Dallas 1-WireÒ interface enables serial
communication on a single battery contact and the
64-bit unique serial number allows multidrop
networking and identification of individual devices.
The 1280-bit memory is organized as 5 pages of 32
bytes each and supports storage of battery cell
characteristics, charging voltage, current, and
temperature parameters, as well as battery pack
manufacturing data. The EEPROM pages are in
circuit rewritable and can be individually locked to
write protect data.
The DS2704 employs the Secure Hash Algorithm
(SHA-1) specified in the Federal Information
publication 180-1 and 180-2, and ISO/IEC 10118-3.
SHA-1 provides a robust cryptographic solution to
ensure battery packs or other peripherals have been
manufactured by authorized sources. The DS2704
processes a host transmitted challenge and the 64-
bit secret key stored on chip to produce a 160-bit
response for transmission back to the host. The
secret key is never transmitted between the battery
and the host.
APPLICATION EXAMPLE
PACK+
150W
DATA
150W
THM
V DD
DQ
DS2704
4.7V
VSS
PACK-
0.01mF
Li+
Safety
Circuit
PIN CONFIGURATION
VDD 1
6 DQ
NC 2
5 VSS
NC 3
4 NC
3mm × 3mm TDFN
(TOP VIEW¾PADS ON BOTTOM)
Top Side A1 Mark
12 3
A
B 1.73
C
1.98 mm
UCSP (FUTURE AVAILABILITY)
(TOP VIEW¾BALLS ON BOTTOM)
FEATURES
§ Secure Challenge and Response Authentication
Using the SHA-1 Algorithm
§ Five Lockable 32-Byte Pages of EEPROM
§ Dallas 1-Wire Interface with Standard and
Overdrive Communications Speeds
§ Unique 64-Bit Serial Number
§ Compatible with DS2502 Memory Map and Read
Function Command
§ Operates with VDD as Low as 2.5V
§ Tiny Chip-Scale UCSP and 3mm x 3mm TDFN
Packaging (Pb-free)
ORDERING INFORMATION
PART
TEMP RANGE
DS2704G+
-20°C to +70°C
DS2704G+T&R
DS2704W
-20°C to +70°C
-20°C to +70°C
PIN-PACKAGE
6-TDFN
DS2704G+ on Tape-and-Reel
Bare Die
+ Denotes lead-free package.
1-Wire is a registered trademark of Dallas Semiconductor.
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DS2704 Datasheet, Funktion
DS2704: 1280-Bit EEPROM with SHA-1 Authentication
Table 1. Authentication Function Commands
COMMAND
Hex FUNCTION
Write Challenge
0C
Writes 64-bit challenge for SHA-1 processing. Required prior to
issuing Compute MAC and Compute Next Secret commands.
Compute MAC without ROM ID
and return MAC
36
Computes hash the message block with logical 1’s in place of the
ROM ID. Returns the 160-bit MAC.
Compute MAC with ROM ID and
return MAC
35
Computes hash of the message block including the ROM ID.
Returns the 160-bit MAC.
SECRET MANAGEMENT FUNCTION COMMANDS
CLEAR SECRET [5Ah]. This command sets the 64-bit secret to all 0’s (0000 0000 0000 0000h). The host must
wait tEEC for the DS2704 to write the new secret value to EEPROM. See Figure 10 on page 18 for command timing.
COMPUTE NEXT SECRET WITHOUT ROM ID [30h]. This command initiates a SHA-1 computation of the MAC
and uses a portion of the resulting MAC as the next or new secret. The MAC computation is performed with the
current 64-bit secret and the 64-bit challenge. Logical 1’s are loaded in place of the ROM ID. 64-bits of the output
MAC are used as the new secret value. The host must allow tSHA after issuing this command for the SHA
calculation to complete, then wait tEEC for the DS2704 to write the new secret value to EEPROM. See Figure 8 on
page 17 for command timing.
COMPUTE NEXT SECRET WITH ROM ID [33h]. This command initiates a SHA-1 computation of the MAC and
uses a portion of the resulting MAC as the next or new secret. The MAC computation is performed with the current
64-bit secret, the 64-bit ROM ID and the 64-bit challenge. 64-bits of the output MAC are used as the new secret
value. The host must allow tSHA after issuing this command for the SHA calculation to complete, then wait tEEC for
the DS2704 to write the new secret value to EEPROM. See Figure 8 on page 17 for command timing.
LOCK SECRET [6Ah]. This command write protects the 64-bit Secret to prevent accidental or malicious overwrite
of the secret value. The Secret value stored in EEPROM becomes "final." The host must wait tEEC for the DS2704
to write the lock secret bit to EEPROM. See Figure 10 on page 18 for command timing.
Table 2. Secret Loading Function Commands
COMMAND
Hex FUNCTION
Clear Secret
5A Clears the 64-bit Secret to 0000 0000 0000 0000h
Compute Next Secret without
ROM ID
Compute Next Secret with
ROM ID
30 Generates new global secret
33 Generates new unique secret
Lock Secret
6A Sets lock bit to prevent changes to the Secret
1-WIRE SPEED CONTROL FUNCTION COMMANDS
CLEAR OVERDRIVE [8Dh]. This command selects the Standard 1-Wire timings shown in the Electrical
Characteristics table. The setting is stored in EEPROM so that the programmed speed selection can be recalled on
initial power up. The host must wait tEEC for the DS2704 to write the EEPROM. See Figure 10 for command timing.
Standard 1-Wire timing is the factory default.
SET OVERDRIVE [8Bh]. This command selects the Overdrive 1-Wire timings shown in the Electrical
Characteristics table. The setting is stored in EEPROM so that the programmed speed selection can be recalled on
initial power up. The host must wait tEEC for the DS2704 to write the EEPROM. See Figure 10 for command timing.
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DS2704 pdf, datenblatt
Figure 4. 1-Wire Bus Interface Circuitry
DS2704: 1280-Bit EEPROM with SHA-1 Authentication
Vpullup
Bus Master
4.7kW
Device 1-Wire Port (DQ)
Rx Rx
~100 Ohm
MOSFET
Tx
Rx = Receive
~1 uA
Tx
Tx = Transmit
TRANSACTION SEQUENCE
The protocol for accessing the DS2704 through the 1-Wire port is as follows:
§ Initialization
§ Net Address Command
§ Function Command(s)
§ Data Transfer (not all commands have data transfer)
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the
bus master, followed by a presence pulse simultaneously transmitted by the DS2704 and any other slaves on the
bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For
more details, see the 1-Wire Signaling section below.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each Net Address command (ROM command) is
followed by the 8-bit opcode for that command in square brackets.
Read Net Address [33h]. This command allows the bus master to read the DS2704’s 1-Wire net address. This
command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision
occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result).
Match Net Address [55h]. This command allows the bus master to specifically address one DS2704 on the 1-Wire
bus. Only the addressed DS2704 responds to any subsequent function command. All other slave devices ignore
the function command and wait for a reset pulse. This command can be used with one or more slave devices on
the bus.
Skip Net Address [CCh]. This command saves time when there is only one DS2704 on the bus by allowing the
bus master to issue a function command without specifying the address of the slave. If more than one slave device
is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at
the same time.
Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the
1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-
step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master
performs this simple three-step routine on each bit location of the net address. After one complete pass through all
64 bits, the bus master knows the address of one device. The remaining devices can then be identified on
additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton® Standards for a comprehensive
discussion of a net address search, including an actual example (www.maxim-ic.com/iButtonBook).
iButton is a registered trademark of Dallas Semiconductor.
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