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PDF DS1372 Data sheet ( Hoja de datos )
| Número de pieza | DS1372 | |
| Descripción | Binary Counter Clock | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev 0; 7/07
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
General Description
The DS1372 is a 32-bit binary up counter and 24-bit
down counter with a unique 64-bit ID. The counters, ID,
configuration, and status registers are accessed using
an I2C serial interface. The DS1372 includes a
SQW/INT open-drain output that can output either a
square wave at one of four predefined frequencies, or it
can output an active-low signal when the 24-bit down
counter reaches 0.
Applications
Portable Audio and Video Players
Pin Configuration
TOP VIEW
+
X1 1
X2 2
AD0 3
DS1372
GND 4
μSOP
8 VCC
7 SQW/INT
6 SCL
5 SDA
Features
♦ Compliant with Microsoft Windows Media® DRM
10 for Portable Devices
♦ 32-Bit Binary Counter
♦ Programmable Alarm
♦ 64-Bit Factory-Programmed ID
♦ Interrupt Output
♦ I2C Serial Interface
♦ Two Selectable I2C Addresses
♦ 2.4V to 5.5V Operating Voltage Range
♦ 1.3V to 5.5V Timekeeping Operating Range
♦ -40°C to +85°C Operating Temperature Range
♦ 8-Pin µSOP
Ordering Information
PART
TEMP RANGE PIN-PACKAGE TOP
MARK
DS1372U+ -40°C to +85°C 8 μSOP
1372
+Denotes a lead-free package. This symbol also appears on the
top mark.
Windows Media is a registered trademark of Microsoft Corp.
Typical Operating Circuit
VCC CRYSTAL VCC
VCC RPU
RPU
CPU
RPU = tR / CB
X1
SCL
X2 VCC
SQW/INT
DS1372
SDA
GND
AD0
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
Detailed Description
The DS1372 is a 32-bit binary counter designed to con-
tinuously count time in seconds. An additional counter
is provided that can generate a periodic alarm. An
interrupt output can be driven when the alarm condition
is met. The device includes a unique, factory-lasered
64-bit ROM ID. The device is programmed serially by
an I2C bidirectional bus.
Oscillator Circuit
The DS1372 is designed to operate with a standard
32.768kHz quartz crystal having a 12.5pF specified
load capacitance (CL). For more information on crystal
selection and crystal layout considerations, refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks (RTCs). An external 32.768kHz oscil-
lator can be used as the DS1372’s time base. In this
configuration, the X1 pin is connected to the external
oscillator signal and the X2 is floated. The EOSC bit in
the Control Register controls oscillator operation.
Clock Accuracy
The initial clock accuracy is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise cou-
pled into the oscillator circuit can result in the clock run-
ning fast. Figure 2 shows a typical PCB layout for
isolation of the crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks (RTCs) for detailed information.
CRYSTAL
X1
X2
LOCAL GROUND PLANE (LAYER 2)
Figure 2. Layout Example
Operation
The block diagram in Figure 1 shows the DS1372’s main
elements. As shown, communications to and from the
DS1372 occur serially over an I2C bidirectional bus. The
DS1372 operates as a slave device on the serial bus.
Access is obtained by implementing a START condition
and providing a device identification code followed by a
register address. Subsequent registers can be accessed
sequentially until a STOP condition is executed.
Address Map
Table 1 shows the address map for the DS1372 regis-
ters. During a multibyte access, when the address
pointer reaches the end of the register space (10h) it
wraps around to location 00h. On an I2C START or
address pointer incrementing to location 00h, the cur-
rent time is transferred to a second set of registers. The
time information is read from these secondary registers,
while the clock may continue to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
Clock Operation
The clock counter is a 32-bit up counter. The counter
counts up once per second. The contents can be read
or written by accessing the address range 00h–03h. On
an I2C START, or when the address pointer rolls over to
00h, the current value is latched into a register, which is
output on the serial data line while the counter contin-
ues to increment. When writing to the registers, the
divider chain is reset when register 00h is written. Once
the divider chain is reset, the remaining clock registers
should be written within one second to avoid rollover
issues. Additionally, to avoid rollover issues the clock
registers must also be written from LSB to MSB, and all
four bytes should always be written.
_______________________________________________________________________________________ 5
5 Page 
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
2) Slave transmitter mode (DS1372 read mode): The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
The DS1372 transmits serial data on SDA while the
serial clock is input on SCL. START and STOP con-
ditions are recognized as the beginning and end of
a serial transfer (see Figure 7). The slave address
byte is the first byte received after the master gener-
ates the START condition. The slave address byte
contains the 7-bit DS1372 address, which is 110100
and AD0. Each slave address is followed by the
direction bit (R/W), which is one for a read. The bit
position signified by A is compared to the value on
the AD0 pin. After receiving and decoding the slave
address byte, the device outputs an acknowledge
on the SDA line. The DS1372 then begins to transmit
data starting with the register address pointed to by
the register pointer. If the register pointer is not writ-
ten to before the initiation of a read mode, the first
address that is read is the last one stored in the reg-
ister pointer. The DS1372 must receive a "not
acknowledge" to end a read.
<SLAVE ADDRESS> <R/W> <WORD ADDRESS (n)>
S 110100 AD0 0 A
XXXXXXXX
A
S - START
A - ACKNOWLEDGE (ACK)
SLAVE TO MASTER
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
<DATA (n)>
<DATA (n + 1)>
<DATA (n + X)
XXXXXXXX A XXXXXXXX A ... XXXXXXXX
MASTER TO SLAVE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
AP
Figure 6. Data Write—Slave Receiver Mode
<SLAVE ADDRESS> <R/W>
S 110100 AD0 1 A
<DATA (n)>
XXXXXXXX
A
S - START
MASTER TO SLAVE
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
<DATA (n + 1)>
<DATA (n + 2)>
<DATA (n + X)>
XXXXXXXX
A
XXXXXXXX
A ...
XXXXXXXX
SLAVE TO MASTER
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
AP
Figure 7. Data Read (from Current Pointer Location)—Slave Transmitter Mode
<SLAVE ADDRESS> <R/W> <WORD ADDRESS (n)> <SLAVE ADDRESS (n)> <R/W>
S 110100A AD0 0 A
XXXXXXXX
A Sr 110100A AD0 1 A
<DATA (n)>
<DATA (n + 1)>
<DATA (n + 2)>
<DATA (n + X)>
XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P
S - START
Sr - REPEATED START
MASTER TO SLAVE
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
SLAVE TO MASTER
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
Figure 8. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS1372.PDF ] | |
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