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PDF DS1123L Data sheet ( Hoja de datos )
| Número de pieza | DS1123L | |
| Descripción | Programmable Timing Element | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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Rev 2; 8/07
3.3V, 8-Bit, Programmable Timing Element
General Description
The DS1123L is an 8-bit programmable timing element
similar in function to the DS1023, but operating at 3.3V.
Like the DS1023, the DS1123L can delay signals up to
a full period or more when used as a delay line, and an
on-chip reference delay can be used to offset the inher-
ent “step-zero” delay. This allows the DS1123L to shift a
clock signal over the full 0 to 360° phase range. In
addition to functioning as a delay line, it can be config-
ured as a free-running oscillator or an externally trig-
gered monostable vibrator.
Features
♦ Step Sizes of 0.25ns, 0.5ns, 1ns, 2ns
♦ On-Chip Reference Delay
♦ Configurable as a Delay Line, Monostable
Vibrator, or Free-Running Oscillator
♦ Can Delay Signals by a Full Period or More
♦ Guaranteed Monotonicity
♦ Parallel and 3-Wire Serial Programming Interface
♦ Single 3.3V Power Supply
♦ 16-pin TSSOP
Applications
Telecommunications
Digital Test Equipment
Digital Video Projection
Signal Generators and Analyzers
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
(150-mil)
STEP SIZE/
NO. OF STEPS
DS1123LE-25
DS1123LE-50
DS1123LE-100
DS1123LE-200
0°C to +70°C 16 TSSOP
0°C to +70°C 16 TSSOP
0°C to +70°C 16 TSSOP
0°C to +70°C 16 TSSOP
0.25/256
0.5/256
1/256
2/256
Typical Operating Circuit
SYSTEM
CLOCK
MICRO-
PROCESSOR
3-WIRE
INTERFACE
IN
LE
(OPTIONAL) Q/P0
CLK/P1
4 D/P2
P3
P4
GND
DS1123L
3.3V
VCC
OUT/OUT
P/S
P7
P6
MS
P5
REF/PWM
VARIABLE
DELAY/PHASE
OUTPUT
REFERENCE
OUTPUT
Pin Configuration
TOP VIEW
IN 1
LE 2
P0/Q 3
P1/CLK 4
P2/D 5
P3 6
P4 7
GND 8
DS1123L
16 VCC
15 OUT/OUT
14 P/S
13 P7
12 P6
11 MS
10 P5
9 REF/PWM
_____________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
3.3V, 8-Bit, Programmable Timing Element
AC ELECTRICAL CHARACTERISTICS (DS1123L-50)
(VCC = +3.0V to 3.6V, TA = 0°C to +70°C.)
PARAMETER
Reference Delay
Delay Step Size
Step-Zero Delay with Respect
to IN
SYMBOL
tREF
tSTEP
(Notes 3, 4)
TA = +25°C
CONDITIONS
tD0 (Notes 4, 5)
Step-Zero Delay with Respect
to REF
tD0REF (Notes 6, 7)
Maximum Delay with Respect
to IN
Delay with Respect to REF
Delay with Respect to REF
Tolerance
Voltage Delay Variation
Temperature Delay Variation
Integral Nonlinearity (Deviation
from Straight Line)
OUT Delta Delay
IN High to PWM High
Minimum PWM Output Pulse
Width
Minimum Input Pulse Width
Minimum Input Period
Input Rise and Fall Times
tDMAX (Notes 4, 8)
tDREF
ΔtDREF
tDREF
ΔtDV
tDREF
ΔtDT
tDREF
Position FF (Notes 7, 9)
VCC = 3.3V, TA = +25°C
(Notes 7, 9)
(Notes 7, 9)
VCC = 3.3V (Notes 7, 9)
terr (Note 10)
tINV0
tPWM0
(Note 11)
(Notes 4, 12)
tPWM (Note 13)
tWI (Note 14)
(Note 15)
tr, tf (Note 16)
MIN TYP
18
0 0.5
16.5
MAX
22
1.75
UNITS
ns
ns
22 ns
-2.5 -1.5
0
ns
-0.75
144
127.5
+0.75
ns
ns
%
-0.75
+0.75
%
-2.5
+2.5
%
-2 0 +2
0 1 2.5
16.5 22
5
40
80
01
ns
ns
ns
ns
ns
ns
µs
_____________________________________________________________________ 5
5 Page 
3.3V, 8-Bit, Programmable Timing Element
tEW
ENABLE
(LE)
CLOCK
(CLK)
SERIAL
INPUT
(D)
SERIAL
INPUT
(Q)
DELAY
TIME
tCW tCW
tES
tEH
tDSC
NEW
BIT 7
tDHC
NEW BIT 6
NEW
BIT 0
tEGV tCQV
tCQX
tEQZ
OLD BIT 7
OLD BIT 6
OLD BIT 0
PREVIOUS VALUE
tEDZ
tEDX
NEW
VALUE
Figure 6. Serial Interface Timing Diagram
to be shifted to U2, U2’s data would be shifted to U3, etc.
As shown, the microprocessor would have to shift 24 bits
during each read or write cycle to avoid inadvertently
changing the settings in any of the 3-wire devices. Also
note that the feedback resistor or a separate input (not
shown) can still be used to read the 3-wire device set-
tings when multiple devices are cascaded.
Configuring the DS1123L as a Delay Line
To use the DS1123L as a delay line, the MS pin must
be tied to ground. When used as a delay line, the inter-
nal architecture of the DS1123L allows the output delay
time to be considerably longer than the input pulse
width (see AC specifications). This feature is useful in
many applications, in particular in clock phase control,
where delays up to and beyond one full clock period
can be achieved. Table 1 lists some of the delay char-
acteristics of the different speed options available for
the DS1123L device.
Using the Reference Delay
All delay lines have an inherent step-zero delay
between IN and OUT (tD0) due to the propagation
delay through the input and output buffers. To simplify
system design, a reference delay has been included on
the DS1123L that can be used to compensate for the
step-zero delay. The reference output allows the
DS1123L to be used to generate small differential
delays that cannot be generated when the OUT delay
is referenced to the input. The step-zero OUT delay is
always approximately 1ns faster than the REF delay
(see Figure 8). This allows the DS1123L to generate a
nondelayed output with respect to the reference output.
In addition, the reference output driver is sized similarly
to the OUT output driver, both outputs act similarly over
temperature, and they are both triggered at the same
time regardless of the exact input threshold. These fea-
tures make the output delay with respect to the refer-
ence act more ideally because both of these outputs
are skewed approximately the same amount due to
these phenomena.
Integral Nonlinearity
Integral nonlinearity (INL) is defined as the deviation from
a straight line response drawn between the measured
step-zero delay and the measured step 255 delay with
respect to the reference output. INL measured with
respect to IN is not specified, but should be slightly high-
er than when measured with respect to the reference out-
put. This is because measurements taken with respect to
____________________________________________________________________ 11
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| PDF Descargar | [ Datasheet DS1123L.PDF ] | |
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