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What is AZP94?

This electronic component, produced by the manufacturer "Arizona Microtek", performs the same function as "Clock Generation Chip".


AZP94 Datasheet PDF - Arizona Microtek

Part Number AZP94
Description Clock Generation Chip
Manufacturers Arizona Microtek　
Logo Arizona Microtek Logo　


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AZP94
ARIZONA MICROTEK, INC.
ECL/PECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs
FEATURES
PACKAGE AVAILABILITY
• Green and RoHS Compliant / Lead (Pb) PACKAGE
PART NO.
Free Package Available
• 3.0V to 5.5V Operation
MLP 8 (2x2) Green
/ RoHS Compliant AZP94NAG
• Selectable Divide Ratio
/ Lead (Pb) Free
MARKING
J4G
<Date Code>
NOTES
1,2
• Selectable Enable Polarity and
DIE
AZP94XP
N/A
3,4
Threshold (CMOS/TTL or PECL)
• Tristate Compatible Outputs
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
• Input Buffer Powers Down when
2 Date code format: “Y” for year followed by “WW” for week.
Disabled
• Selectable Input Biasing
3 Waffle Pack, die thickness 180µ.
4 Contact factory for availability.
• High Bandwidth for ≥1GHz
• Available in a MLP 8 (2x2) Package
• IBIS Model File Available on Arizona
Microtek Website
DESCRIPTION
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If
DIV-SEL is connected to VEE, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or
connected to VEE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to
function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected
which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-
down resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will allow the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). The default logic condition can be overridden by connecting the EN to VCC with an external resistor of
≤20kΩ. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to VEE with
a 20kΩ resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for
details.
When the AZP94 is disabled, the Q and Q¯ outputs are forced LOW and the input buffer is powered down to
minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip
outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive
the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel
connection with PECL/ECL parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when
the outputs are disabled.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com

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AZP94 equivalent
AZP94
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC
VI
VEE
VI
IHGOUT
PECL Power Supply
PECL Input Voltage
ECL Power Supply
ECL Input Voltage
Output Current
(VEE = 0V)
(VEE = 0V)
(VCC = 0V)
(VCC = 0V)
— Continuous
— Surge
0 to +6.0
0 to +6.0
-6.0 to 0
-6.0 to 0
50
100
TA Operating Temperature Range
TSTG Storage Temperature Range
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
Characteristic
-40°C
Min Max
0°C
Min Max
VOH Output HIGH Voltage1 -1085 -880 -1025 -880
VOL Output LOW Voltage1
-1900
-1555
-1900
-1620
Input HIGH Voltage
VIH D/D¯ , EN (ECL)2 -1165 -740 -1165 -740
EN (CMOS)3 VEE+2000 VCC VEE+2000 VCC
Input LOW Voltage
VIL
D/D¯ , EN (ECL)2 -1900
-1475
-1900
-1475
EN (CMOS)3 VEE VEE + 800 VEE VEE + 800
VBB Reference Voltage
-1390
-1250
-1390
-1250
IIH Input HIGH Current EN
150
150
Input LOW Current
IIL
EN (ECL)2
0.5
EN (CMOS)3
-150
0.5
-150
IEE Power Supply Current1
34
34
1. Specified with outputs terminated through 50Ω resistors to VCC - 2V.
2. EN-SEL connected to VEE through a 20kΩ resistor
3. EN-SEL connected VEE or left open (NC)
25°C
Min Max
-1025
-880
-1900
-1620
-1165
VEE+2000
-740
VCC
-1900
VEE
-1390
-1475
VEE + 800
-1250
150
0.5
-150
34
85°C
Min Max
-1025
-880
-1900
-1620
-1165
VEE+2000
-740
VCC
-1900
VEE
-1390
-1475
VEE + 800
-1250
150
0.5
-150
37
Unit
mV
mV
mV
mV
mV
μA
μA
mA
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
Characteristic
-40°C
Min Max
0°C
Min Max
25°C
Min Max
VOH
Output HIGH Voltage1,2
2215
2420
2275
2420
2275
2420
VOL
Output LOW Voltage1,2
1400
1745
1400
1680
1400
1680
Input HIGH Voltage1
VIH
D/D¯ , EN (PECL)3
2135
2560
2135
2560
2135
2560
EN (CMOS)4
2000
VCC
2000
VCC
2000
VCC
Input LOW Voltage1
VIL
D/D¯ , EN (PECL)3
1400
1825
1400
1825
1400
1825
EN (CMOS)4
GND
800
GND
800
GND
800
VBB Reference Voltage1
1910
2050
1910
2050
1910
2050
IIH Input HIGH Current EN
150
150
150
Input LOW Current
IIL
EN (PECL)3
0.5
0.5
0.5
EN (CMOS)4
-150
-150
-150
IEE Power Supply Current2
34
34
34
1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
2. Specified with outputs terminated through 50Ω resistors to VCC - 2V.
3. EN-SEL connected to VEE through a 20kΩ resistor
4. EN-SEL connected VEE or left open (NC)
85°C
Min Max
2275
2420
1400
1680
2135
2000
1400
GND
1910
2560
VCC
1825
800
2050
150
0.5
-150
37
Unit
mV
mV
mV
mV
mV
μA
μA
mA
April 2007 Rev 1
www.azmicrotek.com
5


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AZP94 electronic component.


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