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AZG489 Schematic ( PDF Datasheet ) - Arizona Microtek

Teilenummer AZG489
Beschreibung PECL Video Cable Driver
Hersteller Arizona Microtek
Logo Arizona Microtek Logo 




Gesamt 5 Seiten
AZG489 Datasheet, Funktion
www.DataSheet4U.com
AZG489
ARIZONA MICROTEK, INC.
PECL Video Cable Driver
FEATURES
720 Mb/s Typical Data Rate
1.6V Typical Output Swing
Independent Outputs Operate in Phase
5V±10% Supply Voltage
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE PART NUMBER MARKING NOTES
SOIC 8
AZG489D
AZG489
<Date Code>
1,2
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2 Date Code “YWW” on underside of part.
The AZG489 is a multiple output cable driver specifically designed to drive coaxial video cables. The device is
especially useful in Digital Video Broadcasting applications. Each output has its own output stage and thus each is
isolated from the other outputs.
The driver has a voltage gain of approximately 40 and produces an output swing of 1.6 volts, twice as large as a
standard PECL output. When driving a coaxial cable, proper termination is required at both ends of the cable to
minimize reflections. The 1.6V output signal allows for termination at both ends of the cable, while providing an
800mV signal at the receiving end of the cable.
The driver accepts a standard differential PECL input and can be powered with a 5.0V supply. Under open input
conditions internal input clamps will force all outputs HIGH.
Additional power supply filtering is required because of the large amount of in-phase output current. A
capacitor (0.1μF minimum) must bypass VCC to VEE in close proximity to the AZG489. A ferrite bead (1KΩ @ 100
MHz) must be placed in series to the VEE pin. Additional capacitance may be required based on board layout. See
Figure 1 for further information.
NOTE: The specifications in the PECL table are valid when thermal equilibrium is established. The maximum
junction temperature is 125°C. Thermal management may be required in some applications to ensure the junction
temperature does not exceed that value.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
D, D¯
Q0, Q1, Q2, Q3
VCC
VEE
FUNCTION
PECL Data Inputs
Data Outputs (1.6VPP)
Positive Supply
Negative Supply
Q0 1
Q1 2
Q2 3
Q3 4
8 VCC
7D
6D
5 VEE
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com





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