GSC93BC56 Datasheet PDF - GTM
| Part Number | GSC93BC56 | |
| Description | (GSC93BC46 - GSC93BC66) 2-WIRE SERIAL EEPROMS | |
| Manufacturers | GTM | |
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ISSUED DATE :2006/06/14
REVISED DATE :
GSC93BC46/56/66
3-wire Serial EEPROMs 1K/2K/4K
Description
The GSC93BC family provides 1K, 2K and 4K of serial electrically erasable and programmable read-only
memory (EEPROM). The wide Vdd range allows for low-voltage operation down to 1.8V and up to 5.5V. The
device, fabricated using traditional CMOS EEPROM technology, is optimized for many industrial and
commercial applications where low-voltage and low-power operation is essential. The device is accessed via a
3-wire serial interface.
Features
Internally organized as 128x8 or 64x16 (1K),
256x8 or 128x16 (2K), 512x8 or 256x16 (4K)
Wide-voltage range operation: 1.8V~5.5V
3-wire serial interface bus
Date retention: 100years
High endurance: 1,000,000 Write Cycles
2MHz (5V) clock rate
Sequential read operation
Self-timed write cycle (10ms max)
Package Dimensions
REF.
A
B
C
D
E
F
Millimeter
Min. Max.
5.80
6.20
4.80
5.00
3.80
4.00
0° 8°
0.40
0.90
0.19
0.25
REF.
M
H
L
J
K
G
Millimeter
Min. Max.
0.10
0.25
0.35
0.49
1.35
1.75
0.375 REF.
45°
1.27 TYP.
Figure 1. Pin Configurations
Pin Name
CS
SK
DI
DO
Gnd
Vcc
ORG
NC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
No Connect
Absolute Maximum Ratings
Parameter
Ratings
Unit
Voltage on Any Pin with Respect to Ground
-1.0 to Vcc +7.0
V
Maximum Operating Voltage
6.25 V
DC Output Current
5.0 mA
Operating Temperature Range
-55 ~ +125
Storage Temperature Range
-65 ~ +150
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of
these specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
GSC93BC46/56/66
Page: 1/8
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ISSUED DATE :2006/06/14
REVISED DATE :
ERASE (ERASE): The Erase (ERASE) instruction clears the designated memory location to a logic ‘1’ state.
After the Op Code and address location is inputted, the chip will enter into an erase cycle. When the cycle
completes, the chip will automatically enter into standby mode.
WRITE (WRITE): The Write (WRITE) instruction is used to write to a specific memory location. If word mode
(x16) is selected, then 16 bits of data will be written into the location. If byte mode (x8) is chosen, then 8 bits of
data will be written into the location. The write cycle will begin automatically after the 8 or 16 bits are shifted
into the chip.
ERASE ALL (ERAL): The Erase All (ERAL) instruction is primarily used for testing purposes and only
functions when VCC=4.5V to 5.5V. This instruction will clear the entire memory array to ‘1’.
WRITE ALL (WRAL): The Write All (WRAL) instruction will program the entire memory array according to the 8
or 16-bit data pattern provided. The instruction will only be valid when VCC=4.5V to 5.5V.
ERASE/WRITE DISABLE (EWDS): The Erase/Write Disable (EWDS) instruction blocks any kind of erase or
program operations from modifying the contents of the memory array. This instruction should be executed after
erasing or programming to prevent accidental data loss.
Note also that the READ instruction will operate regardless of whether the chip is disabled from program and
write operations.
Ready/Busy
To determine whether the chip has completed an erase or write operation, the CS signal can be pulled LOW
for a minimum of 250ns (tCS) and then pulled back HIGH to enter Ready/Busy mode. If the chip is currently in
the programming cycle, tWP, then the DO pin will go low (logical “0”). When the write cycle completes, the DO
pin is pulled high (logical “1”) to indicate that the part can receive anther instruction. Note that the Ready/Busy
polling cannot be done if the chip has already finished and returned back to standby mode.
Timing Diagrams
Synchronous Data Timing
Note (1): This is the minimum SK period.
Organization Key for TIMING Diagrams
I/O
GSC93BC46(1K)
GSC93BC56(2K)
X8
AN A6
X16
A5
X8
A8(1)
X16
A7(2)
DN D7
D15 D7
D15
Note:
1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
GSC93BC46/56/66
GSC93BC66(4K)
X8 X16
A8 A7
D7 D15
Page: 5/8
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GSC93BC56 electronic component. |
| Information | Total 8 Pages | |
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| Download | [ GSC93BC56.PDF Datasheet ] | |
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