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PDF AD5024 Data sheet ( Hoja de datos )
| Número de pieza | AD5024 | |
| Descripción | (AD50x4) DAC SPI Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad,
SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Pin compatible and performance upgrade to AD5666
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
3 power-down functions and per-channel power-down
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-/16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAMS
VDD
VREFIN
AD5064-1
SCLK
SYNC
DIN
SDO
LDAC
INTERFACE
LOGIC AND
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
POWER-DOWN
LOGIC
LDAC CLR
POR
GND
Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666
AD5024/
AD5044/
AD5064 LDAC
SCLK
SYNC
DIN
INTERFACE
LOGIC AND
SHIFT
REGISTER
VDD
VREFA VREFB
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
LOGIC
VOUTA
VOUTB
VOUTC
VOUTD
LDAC CLR
POR
VREFC VREFD
GND
Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins
GENERAL DESCRIPTION
The AD5024/AD5044/AD5064/AD5064-1 are low power, quad
12-/14-/16-bit buffered voltage output nanoDAC® converters
that offer relative accuracy specifications of 1 LSB INL and 1 LSB
DNL with the AD5024/AD5044/AD5064 individual reference
pin and the AD5064-1 common reference pin options. The
AD5024/AD5044/AD5064/AD5064-1 can operate from a single
4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1
also offer a differential accuracy specification of ±1 LSB. The
parts use a versatile 3-wire, low power Schmitt trigger serial
interface that operates at clock rates up to 50 MHz and is compati-
ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. Integrated reference buffers and output amplifiers are
also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1
incorporate a power-on reset circuit that ensures the DAC
output powers up to zero scale or midscale and remains there
until a valid write takes place to the device. The AD5024/AD5044/
AD5064/AD5064-1 contain a power-down feature that reduces
the current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power-
down mode. Total unadjusted error for the parts is <2 mV.
PRODUCT HIGHLIGHTS
1. Quad channel available in 14-/16-lead TSSOP packages.
2. 16-bit accurate, 1 LSB INL.
3. High speed serial interface with clock speeds up to 50 MHz.
4. Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Part No.
AD5666
AD5025/AD5045/AD5065
AD5062, AD5063
AD5061
AD5040/AD5060
Description
Quad,16-bit buffered DAC,
16 LSB INL, TSSOP
Dual, 16-bit buffered DACs,
1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, SOT-23,
MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL,
SOT-23
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5024/AD5044/AD5064
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and
Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single Channel Update)
Minimum SYNC High Time (All Channel Update)
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Minimum Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
SCLK Rising Edge to SDO Valid
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update)
SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update)
Power-up Time4
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t8
t9
t10
t11
t12
t13
t14
t152, 3
t162
t172
t182
t182
Min
20
10
10
17
5
5
5
3
8
17
20
20
10
10
10.6
5
8
2
8
4.5
Typ Max
30
22
Unit
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
µs
µs
1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2 Daisy-chain mode only.
3 Measured with the load circuit of Figure 3. t15 determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.
4 Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
Circuit and Timing Diagrams
2mA IOL
TO OUTPUT
PIN CL
50pF
VOH (MIN) + VOL (MAX)
2
2mA IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. F | Page 5 of 28
5 Page 
Data Sheet
0.20
0.15
VDD = 5V
VREF = 4.096V
TA = 25°C
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
512
16,640
32,768
DAC CODE
48,896
Figure 14. Total Unadjusted Error (TUE)
65,024
1.6
1.4 TA = 25°C
1.2
1.0
0.8
0.6 MAX INL ERROR @ VDD = 5.5V
0.4
0.2
0
–0.2
–0.4 MIN INL ERROR @ VDD = 5.5V
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
Figure 15. INL vs. Reference Input Voltage
5.5
1.6
1.4 TA = 25°C
1.2
1.0
0.8
0.6
0.4
0.2 MAX DNL ERROR @ VDD = 5.5V
0
–0.2
–0.4
MIN DNL ERROR @ VDD = 5.5V
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
Figure 16. DNL vs. Reference Input Voltage
5.5
AD5024/AD5044/AD5064
1.2
TA = 25°C
1.0
0.8
0.6
0.4
0.2 MAX TUE @ VDD = 5.5V
0
MIN TUE @ VDD = 5.5V
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
2.0
2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
Figure 17. TUE vs. Reference Input Voltage
5.5
0.015
0.010
0.005
DAC A
0 DAC B
–0.005
DAC D
DAC C
–0.010
VDD = 5.5V
VREF = 4.096V
–0.015
–60 –40 –20
0 20 40 60 80
TEMPERATURE (°C)
100 120 140
Figure 18. Gain Error vs. Temperature
0.6
0.5
DAC C
0.4
0.3
VDD = 5.5V
VREF = 4.096V
0.2
DAC D
0.1
0
–0.1
–0.2
–0.3
DAC A
DAC B
–0.4
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE (ºC)
Figure 19. Offset Error vs. Temperature
Rev. F | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5024.PDF ] | |
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