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Teilenummer | ACD82224 |
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Beschreibung | 24 Ports 10/100 Fast Ethernet Switch | |
Hersteller | ACD | |
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Gesamt 30 Seiten Advanced Communication Devices Corp
ADVANCE INFORMATION
Data Sheet: ACD82224
ACD82224
24 Ports 10/100 Fast Ethernet Switch
Last Update: September 19, 2000
Please check ACD’ s website for update
information before starting a design
Web site: http://www.acdcorp.com
or Contact ACD at:
Email: [email protected]
Tel: 510-354-6810
Fax:510-354-6834
ACD Confidential Material
Use under Non-Disclosure Agreement only. No reproduction or redistribution without ACD’s prior permission.
2. MAJOR FEATURES
• 24 ports 10/100 Fast Ethernet Switch (auto-sensing or manual selection)
• Reduced MII interface, with selectable MII for the last port
• Capable of Trunking for up to 800 Mbps link
• Full & half duplex operation
• Speed auto negotiation through MDIO
• 4.8 Gbps aggregated throughput, true non-blocking switch architecture, full wire speed
forwarding
• Built-in storage of 2,048 MAC address
• Supports up to 11K MAC addresses with the ACD80800
• Shared frame buffer with starvation control
• Memory interface with ZBTTM or compatible SRAM at 100MHz
• Automatic source address learning
• Zero-Packet Loss back-pressure flow control under half duplex mode
• 802.3x pause frame flow control under full duplex mode
• Store-and-forward switch mode
• Port based V-LAN support for up to 4 VLANs
• UART type CPU management interface
• RMON and SNMP support with ACD80900
• Status LEDs: Link, Speed, Full Duplex, Transmit, Receive, Collision, and Frame Error
• 388-pin PBGA package
• Power: core 2.5V, I/O 3.3V with 5V tolerance
3. SYSTEM BLOCK DIAGRAM
PMD/
PHY-0
PMD/
PHY-1
PMD/
PHY-
(xx-2)
PMD/
PHY-
(xx-1)
FIFO
FIFO
FIFO
FIFO
MAC-0
MAC-1
Buffer
Buffer
Buffer
Buffer
FIFO
FIFO
FIFO
FIFO
MAC-
(xx-2)
MAC-
(xx-1)
xx=16 for ACD82216
24 for ACD82224
Buffer
Buffer
Buffer
Buffer
ACD822xx
Lookup Engine
(2K MAC Addr.)
BIST Handler
LED Controller
MX
Queue Manager
DMX
ARL Interface
SRAM Interface
MIB Interface
ARL
ACD80800
(11K MAC Addr.)
(optional)
ZBT or
The Compatible
SRAM
MIB
ACD80900
(optional)
Page 5 of 77
Confidential
Page 5
6 Page Frame Forwarding
If the first bit (bit-40) of the destination address is 0, the frame is handled as a unicast frame.
The destination address is passed to the Address Resolution Logic; which returns a destination
port number to identify which port the frame should be forwarded to. If the Address Resolution
Logic cannot find any match for the destination address, the frame will be treated as a frame with
unknown DA. The frame will be processed in one of two ways upon bit-12of Register 25.
1. If the option flood-to-all-port is set, the switch will forward the frame to all ports within the
same VLAN of the source port, except the source port itself.
2. If the option is not set, the frame will be forwarded to the ‘dumping port’ of the source port
VLAN only. The dumping port is determined by the VLAN ID of the source port. If the source
port belongs to multiple VLANs, a frame with unknown DA will then be forwarded to multiple
dumping ports of the VLANs.
If the first bit of the destination address is a 1, the frame is handled as a multicast or broadcast
frame. The ACD82224 does not differentiate a multicast packet from a broadcast packet except
for the reserved bridge management group address, as specified in Table-3.5 of IEEE 802.1d
standard. The destination ports of a broadcast frame are all ports within the same VLAN except
the source port itself.
The order of all broadcast frames with respect to the unicast frames is strictly enforced by the
ACD82224.
Frame Transmission
The ACD82224 transmits all frames in accordance to IEEE 802.3 standard. The ACD82224 will
send the frames with a guaranteed minimum inter frame gap of 96 BT, even if the received
frames have an IFG less than the minimum requirement. Before the transmitting process is
started, the MAC logic will check if the channel has been silent for more than 64 BT. Within the
64 BT silent window, the transmission process will defer on any receiving process. If the channel
has been silent for more than 64 BT, the MAC will wait an additional 32 BT before starting the
transmitting process. In the event that the carrier sense signal is asserted by the RMII during the
wait period, the MAC logic will generate a JAM signal to cause a forced collision.
The MAC logic will abort the transmitting process if a collision is detected. Re-transmission of the
frame is scheduled in accordance to the IEEE 802.3’s truncated binary exponential back-off
algorithm. If the transmitting process has encountered 16 consecutive collisions, an excessive
collision error is reported, and the ACD82224 will try to re-transmit the frame, unless the drop-on-
excessive-collision option of the port is enabled. It will first reset the number of collisions to zero
and then start the transmission after a 96 BT of inter frame gap. If drop-on-excessive-collision is
enabled, the ACD82224 will not try to re-transmit the frame after 16 consecutive collisions. If
collision is detected after 512 BT of the transmission, a late collision error will be reported and
the frame may or may not be retransmitted.
Shared Buffer
All ports of the ACD82224 work in Store-And-Forward mode so that all ports can support both
10Mbps and 100Mbps data speeds. The ACD82224 utilizes a global memory buffer pool, which
is shared by all ports. The device has a unique architecture that inherits the advantages of both
output buffer-based and input buffer-based switches: short latency of an output-buffer based
switch which only store the received data once into the memory and efficient flow control of an
input-buffer based switch.
Page 11 of 77
Confidential
Page 11
12 Page | ||
Seiten | Gesamt 30 Seiten | |
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