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PDF ACD80800 Data sheet ( Hoja de datos )
| Número de pieza | ACD80800 | |
| Descripción | Address Resolution Logic | |
| Fabricantes | ACD | |
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Advanced
Communication
Devices
Data Sheet: ACD80800
Address Resolution Logic
(8K MAC Addresses)
Rev.1.0.0.E
Last Update: September 19, 2000
Please check ACD’s website for update
information before starting a design
Web site: http://www.acdcorp.com/tech.html
or Contact ACD at:
Email: [email protected]
Tel: 510-354-6810
Fax: 510-354-6834
ACD Confidential Material
For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.
1
1 page  
Lookup Engine of ACD80800. The Address Lookup
Engine checks if the destination address matches with
any existing address in the address table. If it does,
ACD80800 returns the associated Port ID to ACD’s
switch controller through the output data bus. Other-
wise, a no match result is passed to ACD’s switch con-
troller through the output data bus.
CPU Interface
ACD80800 provides a direct input/output type of inter-
face for a management CPU to access various kind of
registers inside ACD80800. The interface has 8-bit data
bus, and 5-bit address bus. The timing of read and
write operation is controlled by output enable signal and
write enable signal. For details of CPU interface timing
information, refer to the section of “Timing Descrip-
tion.”
The CPU can also choose to access the registers of
ACD80800 by sending commands to the UART data
input line. Each command is consisted by action (read
or write), register type, register index, and data. Each
result of command execution is returned to the CPU
through the UART data output line.
CPU Interface Registers
ACD80800 provides a bunch of registers for the control
CPU. Through the registers, the CPU can read all ad-
dress entries of the address table, delete particular ad-
dresses from the table, add particular addresses into
the table, secure an address from being changed, set
filtering on some addresses, change the hashing algo-
rithm etc. Through a proper interrupt request signal, the
CPU can be notified whenever it needs to retrieve data
for a newly-learned address or an aged-out address so
that the CPU can build an exact same address table
learned by ACD80800.
CPU Interface Engine
The command sent by the control CPU is executed by
the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned ad-
dress. The CPU Interface Engine is responsible to find
the newly-learned address from the address table, and
passes it to CPU. The CPU may request to learn next
newly-learned address. Then, it is again the responsi-
bility of the CPU Interface Engine to search for next
newly-learned address from the address table.
Address Table
The address table can hold up to 8K MAC addresses,
together with the associated port ID, security flag, filter-
ing flag, new flag, aging information etc. The address
table resides in the embedded SRAM inside ACD80800.
5
5 Page 
Table-5: Command List
Command
Description
0x09
Add the specified MAC address into the
address table
0x0A
Set a lock for the specified MAC address
0x0B
0x0C
Set a filtering flag for the specified MAC
address
Delete the specified MAC address from
the address table
0x0D
Assign a port ID to the specified MAC
address
0x10
Read the first entry of the address table
0x11
Read next entry of address book
0x20
Read first valid entry
0x21
Read next valid entry
0x30
Read first new page
0x31
Read next new page
0x40
Read first aged page
0x41
Read next aged page
0x50
Read first locked page
0x51
Read next locked page
0x60
Read first filtered page
0x61
Read next filtered page
0x80
Read first page with specified PID
0x81
Read next page with specified PID
0xFF
System reset
The RstReg is used to indicate the status of command
execution. The result code is listed as follows:
• 01 - command is being executed and is
not done yet
• 10 - command is done with no error
• 1x - command is done, with error indi-
cated by x, where x is a 4-bit error code:
0001 for cannot find the entry as speci-
fied
The CfgReg is used to configure the way the
ACD80800 works. The bit definition of CfgReg is
described as:
• bit 0 - disable address aging
• bit 1 - disable address lookup
• bit 2 - disable DA cache
• bit 3 - disable SA cache
• bit 7:4 - hashing algorithm selection,
default is 0000
The IntSrcReg is used to indicate what can cause
interrupt request to CPU. The source of interrupt is
listed as:
• bit 0 - aged address exists
• bit 1 - new address exists
• bit 2 - reserved
• bit 3 - reserved
• bit 4 - bucket overflowed
• bit 5 - command is done
• bit 6 - system initialization is completed
• bit 7 - self test failure
The IntMskReg is used to enable an interrupt source
to generate an interrupt request. The bit definition is
the same as IntSrcReg. A 1 in a bit enables the
corresponding interrupt source to generate an
interrupt request once it is set.
The nLearnReg[2:0] are used to disable address
learning activity from a particular port. If the bit
corresponding to a port is set, ACD80800 will not try
to learn new addresses from that port.
The AgeTimeReg[1:0] are used to specify the period
of address aging control. The aging period can be
from 0 to 65535 units, with each unit counted as 2.684
second.
The PosCfgReg0 is a configuration register whose
default value is determined by the pull-up or pull-down
status of the associated hardware pin. The bits of
PosCfgReg0 is listed as follows:
• bit 0 - BISTEN, shared with ARLDO0, 0
for no self test, 1 for enable self test
• bit 1 - TESTEN, shared with ARLDO1, 0
for normal operation, 1 for production
test.
• bit 2 - DIOEN, shared with ARLDO2, 0 for
using UART, 1 for using DIO.
• bit 3 - SYNCEN, shared with ARLDO3, 0
for using SWPID, 1 for using SWSYNC.
• bit 4 - NOCPU*, 0 for have a control CPU,
1 for do not have a control CPU.
Note: When NOCPU is set as 0, ACD80800 will not
start the initialization process until a System Start
command is sent to the command register.
The PosCfgReg1 is a configuration register whose
default value is determined by the pull-up or pull-down
status of the associated hardware pin. The bits of
PosCfgReg1 is listed as follows:
• bit 1:0 - BUSMODE, shared with
CPUD1:CPUD0, bus width selection, 01
for 48-bit, 10 for 64 bit.
• bit 2 - CPUGO, shared with CPUD2, only
effective when NOCPU bit of PosCfgReg0
is set to 1. Setting CPUGO to 0 means
11
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