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33989 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer 33989
Beschreibung System Basis Chip
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
33989 Datasheet, Funktion
www.DFaretaeSshceeatl4eUS.ceommiconductor
Technical Data
System Basis Chip with
High-Speed CAN Transceiver
Document Number: MC33989
Rev. 13.0, 3/2007
33989
The 33989 is a monolithic integrated circuit combining many
functions used by microcontrollers (MCU) found in automotive
Engine Control Units (ECUs). The device incorporates
functions such as: two voltage regulators, four high voltage
(wake up) inputs, a 1Mbaud capable CAN physical interface,
an SPI interface to the MCU and VSUP monitoring and fault
detection circuitry. The 33989 also provides reset control in
conjunction with VSUP monitoring and the watchdog timer
features. Also, an Interrupt can be generated, for the MCU,
based on CAN bus activity as well as mode changes.
Features
• VDD1: Low Drop Voltage Regulator, Current Limitation,
Overtemperature Detection, Monitoring, and Reset Function
• VDD1: Total Current Capability 200 mA
• V2: Tracking Function of VDD1 Regulator. Control Circuitry for
External Bipolar Ballast Transistor for High Flexibility in Choice of
Peripheral Voltage and Current Supply
• Low Stand-By Current Consumption in Stop and Sleep Modes
• High-Speed 1 MBaud CAN Physical Interface
• Four External High Voltage Wake-up Inputs Associated with HS1
VBAT Switch
• 150 mA Output Current Capability for HS1 VBAT Switch Allowing
Drive of External Switches Pull-Up Resistors or Relays
• VSUP Failure Detection
• 40 V Maximum Transient Voltage
• Pb Free designated by suffix code EG
SYSTEM BASIS CHIP
WITH HIGH-SPEED CAN
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42345B
28-PIN SOICW
ORDERING INFORMATION
Device
MC33989DW/R2
MCZ33989EG/R2
Temperature
Range (TA)
-40°C to 125°C
Package
28 SOICW
33989
VPWR
5.0 V
VDD1
VSUP
V2
MCU
GND
RST
INT
V2CTRL
V2
HS1
Local Module Supply
CS CS
SCLK SPI SCLK
MOSI
MOSI
MISO
MISO
L0
L1
L2
Wake-Up Inputs
L3
WD Safe Circuits
TX CANH
RX CANL
Twisted
CAN Bus
Pair
Figure 1. MC33989 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007. All rights reserved.






33989 Datasheet, Funktion
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
POWER INPUT (VSUP)
Nominal DC Supply Voltage Range
Extended DC Voltage Range 1
Reduced Functionality (8)
Extended DC Voltage Range 2 (9)
Input Voltage During Load Dump
Load Dump Situation
VSUP 5.5 — 18 V
VSUPEX1
V
4.5 — 5.5
VSUPEX2
18
27
V
VSUPLD
V
— — 40
Input Voltage During Jump Start
Jump Start Situation
Supply Current in Standby Mode (10) (11)
IOUT at VDD1 = 40 mA CAN recessive or Sleep-Disable State
Supply Current in Normal Mode (10)
IOUT at VDD1 = 40 mA CAN recessive or Sleep-Disable State
Supply Current in Sleep Mode (10) (11)
VDD1 and V2 OFF, VSUP < 12 V, Oscillator Running (12) CAN in
Sleep-Disable State
Supply Current in Sleep Mode (10) (11)
VDD1 and V2 OFF, VSUP < 12 V, Oscillator Not Running (12) CAN in
Sleep-Disable State
Supply Current in Sleep Mode (10) (11)
VDD1 and V2 OFF, VSUP > 12 V, Oscillator Running (12) CAN in
Sleep-Disable State
Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (10) (11)
VDD1 ON, VSUP < 12 V, Oscillator Running (12) CAN in
Sleep-Disable State
Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (11)
VDD1 ON, VSUP < 12 V, Oscillator Not Running (12) CAN in
Sleep-Disable State
Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (10) (11)
VDD1 ON, VSUP > 12 V, Oscillator Running (12) CAN in
Sleep-Disable State
VSUPJS
ISUP(STDBY)
ISUP(NORM)
ISUP(SLEEP1)
ISUP(SLEEP2)
ISUP(SLEEP3)
ISUP(STOP1)
ISUP(STOP2)
ISUP(STOP3)
— 27
42 45
42.5 45
72 105
57 90
100 150
135 210
130 210
160 230
V
mA
mA
µA
µA
µA
µA
µA
µA
BATFAIL Flag Internal Threshold
VBF
1.5 3.0 4.0
V
Notes
8. VDD1 > 4.0 V, Reset high, Logic pin high level reduced, device is functional.
9. Device is fully functional. All functions are operating. All modes available and operating. Watchdog, HS1 turn ON turn OFF, CAN cell
operating, L0:L3 inputs operating, SPI read/write operation. Overtemperature may occur.
10. Current measured at VSUP pin.
11. With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value.
12. Oscillator running means Forced Wake-up or Cyclic Sense of Software Watchdog is Stop mode are not activated.
33989
6
Analog Integrated Circuit Device Data
Freescale Semiconductor

6 Page









33989 pdf, datenblatt
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max Unit
DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)
SPI Operation Frequency
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
Falling Edge of CS to Rising Edge of SCLK
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time (CL = 220 pF)
MISO Fall Time (CL = 220 pF)
Time from Falling or Rising Edges of CS to:
MISO Low Impedance
MISO High Impedance
Time from Rising Edge of SCLK to MISO Data Valid
0.2 V1 = <MISO> = 0.8 V1, CL = 200 pF
FREQ
0.25
4.0 MHz
tPCLK
250
N/A
ns
tWSCLKH
125
N/A
ns
tWSCLKH
125
N/A
ns
tLEAD
100
N/A
ns
tLAG 100 — N/A ns
tSISU
40
— N/A ns
tSIH 40 — N/A ns
tRSO — 25 50 ns
tFSO — 25 50 ns
tSOEN
ns
tSODIS
50
— — 50
tVALID
ns
— — 50
STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WD, INT)
Delay Between CS Low to High Transition (End of SPI Stop Command) and
Stop Mode Activation Detected by V2 OFF (24)
Interrupt Low Level Duration
SBC in Stop Mode
Internal Oscillator Frequency
All Modes Except Sleep and Stop (24)
Internal Low Power Oscillator Frequency
Sleep and Stop Modes (24)
Watchdog Period 1
Normal and Standby Modes
Watchdog Period 2
Normal and Standby Modes
Watchdog Period 3
Normal and Standby Modes
Watchdog Period 4
Normal and Standby Modes
Watchdog Period Accuracy
Normal and Standby Modes
Notes
24. Guaranteed by design; however it is not production tested.
tCSSTOP
tINT
OSCF1
OSCF2
WD1
WD2
WD3
WD4
f1ACC
18
7.0
8.58
39.6
88
308
-12
— 34
10 13
100 —
100 —
9.75
45
100
350
10.92
50.4
112
392
12
µs
µs
kHz
kHz
ms
ms
ms
ms
%
33989
12
Analog Integrated Circuit Device Data
Freescale Semiconductor

12 Page





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