PDF DS3104-SE Data sheet ( Hoja de datos )

Número de pieza	DS3104-SE
Descripción	Line Card Timing IC
Fabricantes	Maxim Integrated Products
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No Preview Available ! www.DataSheet4U.com Rev: 060507 DS3104-SE Line Card Timing IC with Synchronous Ethernet Support General Description The DS3104-SE is a low-cost, feature-rich timing IC for line cards with synchronous Gigabit Ethernet (GbE), 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports. ITU-T recommendation G.8261 (formerly G.pactiming) specifies that network synchronization can be carried over packet links by synchronizing the bit clock of the physical layer as is currently done on SONET/SDH links. The DS3104-SE enables synchronization in Ethernet line cards in both the transmit and receive directions. In the transmit direction, the device accepts traditional SONET/SDH system clocks such as 19.44MHz from redundant system timing cards and synthesizes frequency-locked xMII clock rates, such as the 125MHz GTX_CLK for GbE GMIIs. Each Ethernet PHY then synthesizes a transmit bit clock that is frequency-locked to the xMII clock, and thus to the system clock and network clock. In the receive direction, each PHY divides down the recovered bit clock to produce the receive xMII clock. The DS3104-SE accepts the xMII clock from any of several Ethernet ports and forwards a frequency-locked system clock, such as 19.44MHz, to the system timing cards. SONET/SDH ports are also supported. Applications Line Cards with Any Mix of Synchronous Ethernet and SONET/SDH Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations Ordering Information PART DS3104GN DS3104GN+ TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 81 CSBGA (10mm)2 81 CSBGA (10mm)2 +Denotes a lead-free/RoHS-compliant package. Features ♦ Timing Card to Line Card Path ♦ Two Input Clocks from Master and Slave Timing Cards (LVDS/LVPECL or CMOS/TTL) ♦ Optional Frame Sync Inputs and Outputs ♦ Continuous Input Clock Quality Monitoring ♦ Hitless Reference Switching, Automatic or Manual ♦ Holdover on Loss of All Inputs ♦ Programmable PLL Bandwidth, 1Hz to 400Hz ♦ Frequency Conversion Between SONET/SDH Rates and Ethernet MII/GMII/XGMII Rates ♦ Up to 7 Output Clocks: 3 CMOS/TTL (≤ 125MHz), 2 LVDS/LVPECL (≤ 312.50MHz), and 2 Dual CMOS/TTL and LVDS/LVPECL ♦ Line Card to Timing Card Path ♦ Up to 8 Input Clocks: 4 CMOS/TTL (≤ 125MHz) and 4 LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz) ♦ Hitless Reference Switching, Automatic or Manual ♦ Frequency Conversion Between Ethernet MII/GMII/XGMII and SONET/SDH Rates ♦ Two Output Clocks to Master and Slave Timing Cards (CMOS/TTL or LVDS/LVPECL) ♦ General ♦ Suitable Line Card IC for Stratum 3/3E/4, SMC, SEC ♦ Numerous Input Clock Frequencies Supported Ethernet xMII: 2.5, 25, 125, 156.25MHz SONET/SDH: 6.48, N x 19.44, N x 51.84MHz PDH: N x DS1, N x E1, N x DS2, DS3, E3 Frame Sync: 2kHz, 4kHz, 8kHz Custom: Any Multiple of 2kHz Up to 131.072MHz, Any Multiple of 8kHz Up to 155.52MHz ♦ Numerous Output Clock Frequencies Supported Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz SONET/SDH: 6.48, N x 19.44, N x 51.84MHz PDH: N x DS1, N x E1, N x DS2, DS3, E3 Other: 10, 10.24, 13, 30.72MHz Frame Sync: 2kHz, 8kHz Custom Clock Rates: Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz ♦ Internal Compensation for Master Clock Oscillator ♦ SPI™ Processor Interface ♦ 1.8V Operation with 2.5V/3.3V I/O (5V Tolerant) ________________________________________________________ Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page www.DataSheet4U.com ________________________________________________________________________________________ DS3104-SE List of Tables Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14 Table 6-3. Global Pin Descriptions ............................................................................................................................ 15 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15 Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16 Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 16 Table 7-1. Input Clock Capabilities ............................................................................................................................ 19 Table 7-2. Locking Frequency Modes ....................................................................................................................... 20 Table 7-3. Default Input Clock Priorities .................................................................................................................... 22 Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 31 Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 35 Table 7-6. Output Clock Capabilities ......................................................................................................................... 37 Table 7-7. Digital1 Frequencies................................................................................................................................. 39 Table 7-8. Digital2 Frequencies................................................................................................................................. 39 Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 40 Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 40 Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 40 Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 41 Table 7-13. OC1–OC7 Output Frequency Selection ................................................................................................. 41 Table 7-14. Standard Frequencies for Programmable Outputs ................................................................................ 42 Table 7-15. External Frame Sync Source ................................................................................................................. 47 Table 8-1. Register Map ............................................................................................................................................ 53 Table 9-1. JTAG Instruction Codes ......................................................................................................................... 119 Table 9-2. JTAG ID Code ........................................................................................................................................ 120 Table 10-1. Recommended DC Operating Conditions ............................................................................................ 121 Table 10-2. DC Characteristics................................................................................................................................ 121 Table 10-3. CMOS/TTL Pins ................................................................................................................................... 122 Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 122 Table 10-5. LVDS Output Pins ................................................................................................................................ 122 Table 10-6. LVPECL Level-Compatible Output Pins............................................................................................... 123 Table 10-7. Input Clock Timing................................................................................................................................ 125 Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 125 Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode............................................................ 125 Table 10-10. SPI Interface Timing ........................................................................................................................... 126 Table 10-11. JTAG Interface Timing........................................................................................................................ 128 Table 10-12. Reset Pin Timing ................................................................................................................................ 129 Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 130 Table 12-1. CSBGA Package Thermal Properties, Natural Convection ................................................................. 132 5 5 Page www.DataSheet4U.com ________________________________________________________________________________________ DS3104-SE 5. Detailed Features 5.1 • • • • • • Input Clock Features Eight input clocks: four CMOS/TTL (≤ 125MHz) and four LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz) CMOS/TTL Input clocks accept any multiple of 2kHz up to 125MHz LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25MHz All input clocks are constantly monitored by programmable activity monitors Fast activity monitor can disqualify the selected reference after two missing clock cycles Three optional 2/4/8kHz frame-sync inputs for frame-sync signals from master and slave timing cards and an optional backup timing source 5.2 • • • • • • • • • • • • • • • • Timing Card to Line Card DPLL Features (T0 DPLL) High-resolution DPLL plus two or three low-jitter output APLLs Sophisticated state machine automatically transitions between free-run, locked, and holdover states Revertive or nonrevertive reference selection algorithm Programmable bandwidth from 0.1Hz to 400Hz Separately configurable acquisition bandwidth and locked bandwidth Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 Multiple phase detectors: phase/frequency, early/late, and multicycle Phase/frequency locking (±360° capture) or nearest-edge phase locking (±180° capture) Multicycle phase detection and locking (up to ±8191UI) improves jitter tolerance and lock time Phase build-out in response to reference switching Less than 5 ns output clock phase transient during phase build-out Output phase adjustment up to ±200ns in 6ps steps with respect to selected input reference High-resolution frequency and phase measurement Holdover frequency averaging over 1 second interval Fast detection of input clock failure and transition to holdover mode Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks 5.3 • • • • • • • • • • • Line Card to Timing Card DPLL Features (T4 DPLL) High-resolution DPLL plus low-jitter output APLL Programmable bandwidth from 18Hz to 70Hz Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 Multiple phase detectors: phase/frequency, early/late, and multicycle Phase/frequency locking (±360° capture) or nearest-edge phase locking (±180° capture) Multicycle phase detection and locking (up to ±8191UI) improves jitter tolerance and lock time 2kHz and 8kHz frame syncs with programmable polarity and pulse width Can operate independently or locked to T0 DPLL Phase detector can be used to measure phase difference between two input clocks Optional PLL bypass mode provides input clock monitoring, selection, and optional frequency division but bypasses the DPLL and APLL when they aren’t needed (e.g., dividing an input clock to 8kHz) High-resolution frequency and phase measurement 11 11 Page

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