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PDF DS1865 Data sheet ( Hoja de datos )
| Número de pieza | DS1865 | |
| Descripción | PON Triplexer Control and Monitoring Circuit | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev 0; 3/07
PON Triplexer Control and
Monitoring Circuit
General Description
The DS1865 controls and monitors all the burst-mode
transmitter and video receiver biasing functions for a
passive optical network (PON) triplexer. It has an APC
loop with tracking-error compensation that provides the
reference for the laser driver bias current and a temper-
ature-indexed lookup table (LUT) that controls the mod-
ulation current. It continually monitors for high output
current, high bias current, and low and high transmit
power with its internal fast comparators to ensure that
laser shutdown for eye safety requirements are met with-
out adding external components. Six ADC channels
monitor VCC, internal temperature, and four external
monitor inputs (MON1–MON4) that can be used to meet
transmitter and video receive signal monitoring require-
ments. Two digital-to-analog converter (DAC) outputs
are available for biasing the video receiver channel, and
five digital I/O pins are present to allow additional moni-
toring and configuration.
Applications
Optical Triplexers with GEPON, BPON, or GPON
Transceiver
Pin Configuration
TOP VIEW
28 27 26 25 24 23 22
BEN 1
TX-D 2
TX-F 3
FETG 4
VCC 5
GND 6
N.C. 7
DS1865
21 MOD
20 BIAS
19 VCC
18 GND
17 M4DAC
16 DAC1
15 MON4
8 9 10 11 12 13 14
TQFN
(5mm x 5mm x 0.8mm)
Features
o Meets GEPON, BPON, and GPON Timing
Requirements for Burst-Mode Transmitters
o Bias Current Control Provided by APC Loop with
Tracking-Error Compensation
o Modulation Current is Controlled by a
Temperature-Indexed Lookup Table
o Laser Power Leveling from -6dB to +0dB
o Two 8-Bit Analog Outputs, One is Controlled by
MON4 Voltage for Video Amplifier Gain Control
o Internal Direct-to-Digital Temperature Sensor
o Six Analog Monitor Channels: Temperature, VCC,
MON1, MON2, MON3, and MON4
o Five Digital I/O Pins for Additional Control and
Monitoring Functions
o Comprehensive Fault Management System with
Maskable Laser Shutdown Capability
o Two-Level Password Access to Protect
Calibration Data
o 120 Bytes of Password 1 Protected Nonvolatile
Memory
o 128 Bytes of Password 2 Protected Nonvolatile
Memory in Main Device Address
o 128 Bytes of Nonvolatile Memory Located at A0h
Slave Address
o I2C-Compatible Interface for Calibration and
Monitoring
o Operating Voltage: 2.85V to 5.5V
o Operating Temperature Range: -40°C to +95°C
o Packaging: 28-Pin Lead-Free TQFN (5mm x 5mm
x 0.8mm)
Ordering Information
PART
DS1865T+
TEMP RANGE
-40°C to +95°C
DS1865T+T&R -40°C to +95°C
+Denotes lead-free package.
*EP = Exposed pad.
PIN-PACKAGE
28 TQFN-EP*
(5mm x 5mm x 0.8mm)
28 TQFN-EP*
(5mm x 5mm x 0.8mm)
tape-and-reel
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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PON Triplexer Control and
Monitoring Circuit
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 9.)
PARAMETER
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and
START Condition
Start Hold Time
Start Setup Time
Data in Hold Time
SYMBOL
fSCL
tLOW
tHIGH
(Note 11)
tBUF
tHD:STA
tSU:STA
tHD:DAT
CONDITIONS
MIN
0
1.3
0.6
1.3
0.6
0.6
0
Data in Setup Time
tSU:DAT
100
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
STOP Setup Time
Capacitive Load for Each Bus Line
EEPROM Write Time
tR (Note 12)
tF (Note 12)
tSU:STO
CB
tW
(Note 12)
(Note 13)
20 +
0.1CB
20 +
0.1CB
0.6
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
µs
0.9 µs
ns
300 ns
300 ns
µs
400 pF
20 ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +5.5V)
PARAMETER
SYMBOL
CONDITIONS
EEPROM Write Cycles
At +70°C
MIN TYP
50,000
MAX UNITS
Note 1: All voltages are referenced to ground. Current into IC is positive, out of the IC is negative.
Note 2: Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. DAC1 and M4DAC are not loaded.
Note 3: See the Safety Shutdown (FETG) Output section for details.
Note 4: Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5: This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6: Eight ranges allow the BMD full-scale range to change from 312.5mV to 1.25V.
Note 7: The output impedance of the DS1865 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
Note 8: This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9: See the APC and Quick-Trip Shared Comparator Timing section for details.
Note 10: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be 1% within the time specified by the binary search time. See the Bias and MOD Output During
Power-Up section.
Note 11: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with the I2C stan-
dard mode.
Note 12: CBtotal capacitance of one bus line in picofarads.
Note 13: EEPROM write begins after a STOP condition occurs.
Note 14: Guaranteed by design.
_____________________________________________________________________ 5
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PON Triplexer Control and
Monitoring Circuit
The APC loop’s feedback is the monitor diode (BMD)
current, which is converted to a voltage using an exter-
nal resistor. The feedback voltage is compared to an 8-
bit scaleable voltage reference that determines the
APC set point of the system. Scaling of the reference
voltage accommodates the wide range in photodiode
sensitivities. This allows the application to take full
advantage of the APC reference’s resolution.
The DS1865 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
tracking error (TE). The TE LUT (Table 05h) has 36
entries that determine the APC setting in 4°C windows
between -40°C to +100°C. Ranging of the APC DAC is
possible by programming a single byte in Table 02h.
Modulation Control
The MOD output is an 8-bit scaleable voltage output that
interfaces with the MAX3643’s VMSET input. An external
resistor to ground from the MAX3643’s MODSET pin sets
the maximum current the voltage at VMSET input can
produce for a given output range. This resistor value
should be chosen to produce the maximum modulation
current the laser type requires over temperature. Then
the MOD output’s scaling is used to calibrate the full-
scale (FS) modulation output to a particular laser’s
requirements. This allows the application to take full
advantage of the MOD output’s resolution. The modula-
tion LUT can be programmed in 2°C increments over the
-40°C to +102°C range.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h.
BIAS and MOD Output
During Power-Up
On power-up, the modulation and bias outputs remain
off until VCC is above VPOA and a temperature conver-
sion has been completed. If the VCC LO ADC alarm is
enabled, then a VCC conversion above the customer-
defined VCC low alarm level is required before the
outputs are enabled with the value determined by the
temperature conversion and the modulation LUT.
When the MOD output is enabled and BEN is high, the
BIAS output is turned on to a value equal to ISTEP (see
Figure 1). The startup algorithm checks if this bias cur-
rent causes a feedback voltage above the APC set point,
and if it does not it continues increasing the BIAS by
ISTEP until the APC set point is exceeded. When the APC
set point is exceeded, the DS1865 begins a binary
search to quickly reach the bias current corresponding
to the proper power level. After the binary search is com-
pleted the APC integrator is enabled, and single LSB
steps are taken to tightly control the average power.
All quick-trip alarm flags are masked until the binary
search is completed. However, the BIAS MAX alarm is
monitored during this time to prevent the bias output
from exceeding MAX IBIAS. During the bias current ini-
tialization, the bias current is not allowed to exceed
MAX IBIAS. If this occurs during the ISTEP sequence,
the binary search routine begins. If MAX IBIAS is
exceeded during the binary search, the next smaller
step is activated. ISTEP or binary increments that would
cause IBIAS to exceed MAX IBIAS are not taken.
Masking the alarms until the completion of the binary
search prevents false trips during startup.
ISTEP is programmed by the customer using the Startup
Step register. This value should be programmed to the
maximum safe current increase that is allowable during
startup. If this value is programmed too low, the DS1865
will still operate, but it could take significantly longer for
the algorithm to converge and hence to control the aver-
age power.
If a fault is detected and TX-D is toggled to re-enable the
outputs, the DS1865 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1865 already has determined the present tem-
perature, so the tINIT time is not required for the DS1865
to recall the APC and MOD set points from EEPROM.
If the Bias-En bit (Table 02h, Register 80h) is written to
0, the BIAS DAC is manually controlled by the MAN
IBIAS register (Table 02h, Registers F8h–F9h).
BIAS and MOD Output as a Function
of Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal oper-
ation, the outputs are disabled within tOFF. When TX-D
is deasserted (logic 0), the DS1865 turns on the MOD
output with the value associated with the present tem-
perature, and initializes the BIAS using the same
search algorithm used at startup. When asserted, the
soft TX-D (Lower Memory, Register 6Eh) offers a soft-
ware control identical to the TX-D pin (see Figure 2).
APC and Quick-Trip Shared
Comparator Timing
As shown in Figure 3, the DS1865’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP-HI, TXP-LO, and BIAS HI). The
comparator polls the alarms in a round-robin multi-
plexed sequence. Six of every eight comparator read-
ings are used for APC loop-bias current control. The
other two updates are used to check the HTXP/LTXP
(monitor diode voltage) and the HBIAS (MON1) signals
against the internal APC and BIAS reference. The
HTXP/LTXP comparison checks HTXP to see if the last
____________________________________________________________________ 11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS1865.PDF ] | |
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